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? 2007 microchip technology inc. preliminary ds39881b pic24fj64ga004 family data sheet 28/44-pin general purpose, 16-bit flash microcontrollers
ds39881b-page ii preliminary ? 2007 microchip technology inc. information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , k ee l oq logo, micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic, and smartshunt are registered tr ademarks of microchip technology incorporated in the u.s.a. and other countries. amplab, filterlab, linear active thermistor, migratable memory, mxdev, mxlab, ps logo, seeval, smartsensor and the embedded control solutions company are registered trademarks of micr ochip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powe rtool, real ice, rflab, rfpicdem, select mode, smart serial, smarttel, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2007, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvi ng the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona, gresham, oregon and mountain view, california. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
? 2007 microchip technology inc. preliminary ds39881b-page 1 pic24fj64ga004 family high-performance cpu: ? modified harvard architecture ? up to 16 mips operation @ 32 mhz ? 8 mhz internal oscillator with 4x pll option and multiple divide options ? 17-bit by 17-bit single-cycle hardware multiplier ? 32-bit by 16-bit hardware divider ? 16-bit x 16-bit working register array ? c compiler optimized instruction set architecture: - 76 base instructions - flexible addressing modes ? two address generation units for separate read and write addressing of data memory special microcontroller features: ? operating voltage range of 2.0v to 3.6v ? 5.5v tolerant input (digital pins only) ? high-current sink/source (18 ma/18 ma) on all i/o pins ? flash program memory: - 10,000 erase/write - 20-year data retention minimum ? power management modes: - sleep, idle, doze and alternate clock modes - operating current 650 a/mips typical at 2.0v - sleep current 150 na typical at 2.0v ? fail-safe clock monitor operation: - detects clock failure and switches to on-chip, low-power rc oscillator ? on-chip, 2.5v regulator with tracking mode ? power-on reset (por), power-up timer (pwrt) and oscillator start-up timer (ost) ? flexible watchdog timer (wdt) with on-chip, low-power rc oscillator for reliable operation ? in-circuit serial programming? (icsp?) and in-circuit debug (icd) via 2 pins ? jtag boundary scan and programming support analog features: ? 10-bit, up to 13-channel analog-to-digital converter: - 500 ksps conversion rate - conversion available during sleep and idle ? dual analog comparators with programmable input/output configuration peripheral features: ? peripheral pin select: - allows independent i/o mapping of many peripherals - up to 26 available pins (44-pin devices) - continuous hardware integrity checking and safety interlocks prevent unintentional configuration changes ? 8-bit parallel master/slave port (pmp/psp): - up to 16-bit multiplexed addressing, with up to 11 dedicated address pins on 44-pin devices - programmable polarity on control lines ? hardware real-time clock/calendar (rtcc): - provides clock, calendar and alarm functions ? programmable cyclic redundancy check (crc) ? two 3-wire/4-wire spi modules (support 4 frame modes) with 8-level fifo buffer ?two i 2 c? modules support multi-master/slave mode and 7-bit/10-bit addressing ? two uart modules: - supports rs-485, rs-232, and lin 1.2 - on-chip hardware encoder/decoder for irda ? - auto-wake-up on start bit - auto-baud detect - 4-level deep fifo buffer ? five 16-bit timers/counters with programmable prescaler ? five 16-bit capture inputs ? five 16-bit compare/pwm outputs ? configurable open-drain outputs on digital i/o pins ? up to 4 external interrupt sources pic24fj device pins program memory (bytes) sram (bytes) remappable peripherals i 2 c? 10-bit a/d (ch) comparators pmp/psp jtag remappable pins timers 16-bit capture input compare/ pwm output uart w/ irda ? spi 16ga002 28 16k 4k 16 5 5 5 2 2 2 10 2 y y 32ga002 28 32k 8k 16 5 5 5 2 2 2 10 2 y y 48ga002 28 48k 8k 16 5 5 5 2 2 2 10 2 y y 64ga002 28 64k 8k 16 5 5 5 2 2 2 10 2 y y 16ga004 44 16k 4k 26 5 5 5 2 2 2 13 2 y y 32ga004 44 32k 8k 26 5 5 5 2 2 2 13 2 y y 48ga004 44 48k 8k 26 5 5 5 2 2 2 13 2 y y 64ga004 44 64k 8k 26 5 5 5 2 2 2 13 2 y y 28/44-pin genera l purpose, 16-bit fl ash microcontrollers
pic24fj64ga004 family ds39881b-page 2 preliminary ? 2007 microchip technology inc. pin diagrams pic24fjxxga002 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 28-pin spdip, ssop, soic (1) 28-pin qfn (1) 10 11 2 3 6 1 18 19 20 21 22 12 13 14 15 8 7 16 17 23 24 25 26 27 28 9 pic24fjxxga002 5 4 mclr v ss v dd an0/v ref +/cn2/ra0 an1/v ref -/cn3/ra1 pgd1/emud1/an2/c2in-/ rp0 /cn4/rb0 sosco/t1ck/cn0/pma1/ra4 sosci/ rp4 /pmbe/cn1/rb4 osco/clko/cn29/pma0/ra3 osci/clki/cn30/ra2 an5/c1in+/ rp3 /scl2/cn7/rb3 an4/c1in-/ rp2 /sda2/cn6/rb2 pgc1/emuc1/an3/c2in+/ rp1 /cn5/rb1 pgd3/emud3/ rp5 /sda1 (2) /cn27/x/rb5 v dd v ss pgc3/emuc3/ rp6 /scl1 (2) /cn24/pmd6/rb6 disvreg v cap /v ddcore rp7 /int0/cn23/pmd5/rb7 tdo/ rp9 /sda1/cn21/pmd3/rb9 tck /rp8 /scl1/cn22/pmd4/rb8 an9/ rp15 /cn11/pmcs1/rb15 an10/cv ref /rtcc/ rp14 /cn12/pmwr/rb14 an11/ rp13 /cn13/pmrd/rb13 an12/ rp12 /cn14/pmd0/rb12 pgd2/emud2/tdi/ rp10 /cn16/pmd2/rb10 pgc2/emuc2/tms/ rp11 /cn15/pmd1/rb11 v ss pgd1/emud1/an2/c2in-/ rp0 /cn4/rb0 osco/clko/cn29/pma0/ra3 osci/clki/cn30/ra2 an5/c1in+/ rp3 /scl2/cn7/rb3 an4/c1in-/ rp2 /sda2/cn6/rb2 pgc1/emuc1/an3/c2in+/ rp1 /cn5/rb1 disvreg v cap /v ddcore tdo/ rp9 /sda1/cn21/pmd3/rb9 an11/ rp13 /cn13/pmrd/rb13 an12/ rp12 /cn14/pmd0/rb12 pgd2/emud2/tdi/ rp10 /cn16/pmd2/rb10 pgc2/emuc2/tms/ rp11 /cn15/pmd1/rb11 v dd pgc3/emuc3/ rp6 /scl1 (2) /cn24/pmd6/rb6 sosco/t1ck/cn0/pma1/ra4 sosci/ rp4 /pmbe/cn1/rb4 rp7 /int0/cn23/pmd5/rb7 tck/ rp8 /scl1/cn22/pmd4/rb8 pgd3/emud3/ rp5 /sda1 (2) /cn27/pmd7/rb5 mclr an0/v ref +/cn2/ra0 an1/v ref -/cn3/ra1 v dd v ss an9/ rp15 /cn11/pmcs1/rb15 an10/cv ref /rtcc/ rp14 /cn12/pmwr/rb14 legend: rpn represents remappable peripheral pins. note 1: rpn pins can be configured to function as any of the fo llowing peripherals: timers, uart, input capture, output compare, pwm, comparator digital outputs and spi. for more information, see section 9.4 ?peripheral pin select? and the specific peripheral sections. 2: alternative multiplexing for sda1 and scl1 when i2c1sel configuration bit is cleared.
? 2007 microchip technology inc. preliminary ds39881b-page 3 pic24fj64ga004 family pin diagrams (continued) 10 11 2 3 4 5 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 pic24fjxxga004 37 44-pin qfn rp8 /scl1/cn22/pmd4/rb8 rp7 /int0/cn23/pmd5/rb7 pgc3/emuc3/ rp6 /scl1 (2) / cn24/pmd6/rb6 pgd3/emud3/ rp5 /sda1 (2) / cn27/pmd7/rb5 v dd tdi/pma9/ra9 sosco/t1ck/cn0/ra4 v ss rp21 /cn26/pma3/rc5 rp20 /cn25/pma4/rc4 rp19 /cn28/pmbe/rc3 an12/ rp12 /cn14/pmd0/rb12 pgc2/emuc2/ rp11 /cn15/pmd1/rb11 pgd2/emud2/ rp10 /cn16/pmd2/rb10 v cap /v ddcore disvreg rp25 /cn19/pma6/rc9 rp24 /cn20/pma5/rc8 rp23 /cn17/pma0/rc7 rp22 /cn18/pma1/rc6 rp9 /sda1/cn21/pmd3/rb9 an11/ rp13 /cn13/pmrd/rb13 an4/c1in-/ rp2 /sda2/cn6/rb2 an5/c1in+/ rp3 /scl2/cn7/rb3 an6/ rp16 /cn8/rc0 an7/ rp17 /cn9/rc1 an8/ rp18 /cn10/pma2/rc2 sosci/ rp4 /cn1/rb4 v dd v ss osci/clki/cn30/ra2 osco/clko/cn29/ra3 tdo/pma8/ra8 pgc1/emuc1/an3/c2in+/ rp1 /cn5/rb1 pgd1/emud1/an2/c2in-/ rp0 /cn4/rb0 an1/v ref -/cn3/ra1 an0/v ref +/cn2/ra0 mclr tms/pma10/ra10 av dd av ss an9/ rp15 /cn11/pmcs1/rb15 an10/cv ref /rtcc/ rp14 /cn12/pmwr/rb14 tck/pma7/ra7 legend: rpn represents remappable peripheral pins. note 1: rpn pins can be configured to function as any of the following peripherals: timers, uart, input capture, output compare, pwm, comparator digital outputs and spi. for more information, see section 9.4 ?peripheral pin select? and the specific peripheral sections. 2: alternative multiplexing for sda1 and scl1 when i2c1sel configuration bit is cleared.
pic24fj64ga004 family ds39881b-page 4 preliminary ? 2007 microchip technology inc. pin diagrams (continued) 10 11 2 3 4 5 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 37 44-pin tqfp pic24fjxxga004 an12/ rp12/ cn14/pmd0/rb12 pgc2/emuc2/ rp11 /cn15/pmd1/rb11 pgd2/emud2/ rp10 /cn16/pmd2/rb10 v cap /v ddcore disvreg rp25 /cn19/pma6/rc9 rp24 /cn20/pma5/rc8 rp23 /cn17/pma0/rc7 rp22 /cn18/pma1/rc6 rp9 /sda1/cn21/pmd3/rb9 an11/ rp13 /cn13/pmrd/rb13 an4/c1in-/ rp2 /sda2/cn6/rb2 an5/c1in+/ rp3 /scl2/cn7/rb3 an6/ rp16 /cn8/rc0 an7/ rp17 /cn9/rc1 an8/ rp18 /cn10/pma2/rc2 sosci/ rp4 /cn1/rb4 v dd v ss osci/clki/cn30/ra2 osco/clko/cn29/ra3 tdo/pma8/ra8 rp8 /scl1/cn22/pmd4/rb8 rp7 /int0/cn23/pmd5/rb7 pgc3/emuc3/ rp6 /scl1 (2) /cn24/pmd6/rb6 pgd3/emud3/ rp5 /sda1 (2) /cn27/pmd7/rb5 v dd tdi/pma9/ra9 sosco/t1ck/cn0/ra4 v ss rp21 /cn26/pma3/rc5 rp20 /cn25/pma4/rc4 rp19 /cn28/pmbe/rc3 pgc1 / emuc1 / an3/c2in+/ rp1 /cn5/rb1 pgd1/emud1/an2/c2in-/ rp0 /cn4/rb0 an1/v ref -/cn3/ra1 an0/v ref +/cn2/ra0 mclr tms/pma10/ra10 av dd av ss an9/ rp15 /cn11/pmcs1/rb15 an10/cv ref /rtcc/ rp14 /cn12/pmwr/rb14 tck/pma7/ra7 legend: rpn represents remappable peripheral pins. note 1: rpn pins can be configured to function as any of the fo llowing peripherals: timers, uart, input capture, output compare, pwm, comparator digital outputs and spi. for more information, see section 9.4 ?peripheral pin select? and the specific peripheral sections. 2: alternative multiplexing for sda1 and scl1 when i2c1sel configuration bit is cleared.
? 2007 microchip technology inc. preliminary ds39881b-page 5 pic24fj64ga004 family table of contents 1.0 device overview ............................................................................................................. ............................................................. 7 2.0 cpu ........................................................................................................................ ................................................................... 17 3.0 memory organization ......................................................................................................... ........................................................ 23 4.0 flash program memory........................................................................................................ ...................................................... 41 5.0 resets ...................................................................................................................... .................................................................. 47 6.0 interrupt controller ........................................................................................................ ............................................................. 53 7.0 oscillator configuration ..................................... ............................................................... .......................................................... 87 8.0 power-saving features....................................................................................................... ....................................................... 95 9.0 i/o ports ................................................................................................................... .................................................................. 97 10.0 timer1 ..................................................................................................................... ................................................................. 117 11.0 timer2/3 and timer4/5 ..................................................................................................... ....................................................... 119 12.0 input capture.............................................................................................................. .............................................................. 125 13.0 output compare............................................................................................................. .......................................................... 127 14.0 serial peripheral interface (spi).......................................................................................... ..................................................... 133 15.0 inter-integrated circuit (i 2 c?) ............................................................................................................................ ..................... 143 16.0 universal asynchronous receiver transmitter (uart) ......................................................................... .................................. 153 17.0 parallel master port (pmp)................................................................................................. ...................................................... 161 18.0 real-time clock and calendar (rtcc) ....................................................................................... ........................................... 171 19.0 programmable cyclic redundancy check (crc) generator ......... .............................................................. ........................... 181 20.0 10-bit high-speed a/d converter............................................................................................ ................................................. 185 21.0 comparator module.......................................................................................................... ........................................................ 195 22.0 comparator voltage reference............................................................................................... ................................................. 199 23.0 special features ........................................................................................................... ........................................................... 201 24.0 development support........................................................................................................ ....................................................... 211 25.0 instruction set summary .................................................................................................... ...................................................... 215 26.0 electrical characteristics ................................................................................................. ......................................................... 223 27.0 packaging information...................................................................................................... ........................................................ 237 appendix a: revision history................................................................................................... .......................................................... 245 index .......................................................................................................................... ....................................................................... 247 the microchip web site ......................................................................................................... ............................................................ 251 customer change notification service ........................................................................................... ................................................... 251 customer support............................................................................................................... ............................................................... 251 reader response ................................................................................................................ .............................................................. 252 product identification system .................................................................................................. .......................................................... 253
pic24fj64ga004 family ds39881b-page 6 preliminary ? 2007 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/doc umentation issues become known to us, we will publis h an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particul ar device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
? 2007 microchip technology inc. preliminary ds39881b-page 7 pic24fj64ga004 family 1.0 device overview this document contains device-specific information for the following devices: ? pic24fj16ga002 ? pic24fj32ga002 ? pic24fj48ga002 ? pic24fj64ga002 ? pic24fj16ga004 ? pic24fj32ga004 ? pic24fj48ga004 ? pic24fj64ga004 this family introduces a new line of microchip devices: a 16-bit microcontroller family with a broad peripheral feature set and enhanced computational performance. the pic24fj64ga004 family offers a new migration option for those high-performance applications which may be outgrowing their 8-bit platforms, but don?t require the numerical processing power of a digital signal processor. 1.1 core features 1.1.1 16-bit architecture central to all pic24f devices is the 16-bit modified harvard architecture, first introduced with microchip?s dspic ? digital signal controllers. the pic24f cpu core offers a wide range of enhancements, such as: ? 16-bit data and 24-bit address paths with the ability to move information between data and memory spaces ? linear addressing of up to 12 mbytes (program space) and 64 kbytes (data) ? a 16-element working register array with built-in software stack support ? a 17 x 17 hardware multiplier with support for integer math ? hardware support for 32 by 16-bit division ? an instruction set that supports multiple addressing modes and is optimized for high-level languages such as ?c? ? operational performance up to 16 mips 1.1.2 power-saving technology all of the devices in the pic24fj64ga004 family incorporate a range of features that can significantly reduce power consumption during operation. key items include: ? on-the-fly clock switching: the device clock can be changed under software control to the timer1 source or the internal, low-power rc oscillator during operation, allowing the user to incorporate power-saving ideas into their software designs. ? doze mode operation: when timing-sensitive applications, such as serial communications, require the uninterrupted operation of peripherals, the cpu clock speed can be selectively reduced, allowing incremental power savings without missing a beat. ? instruction-based power-saving modes: the microcontroller can suspend all operations, or selectively shut down its core while leaving its peripherals active, with a single instruction in software. 1.1.3 oscillator options and features all of the devices in the pic24fj64ga004 family offer five different oscillator options, allowing users a range of choices in developing application hardware. these include: ? two crystal modes using crystals or ceramic resonators. ? two external clock modes offering the option of a divide-by-2 clock output. ? a fast internal oscillator (frc) with a nominal 8 mhz output, which can also be divided under software control to provide clock speeds as low as 31 khz. ? a phase lock loop (pll) frequency multiplier, available to the external oscillator modes and the frc oscillator, which allows clock speeds of up to 32 mhz. ? a separate internal rc oscillator (lprc) with a fixed 31 khz output, which provides a low-power option for timing-insensitive applications. the internal oscillator block also provides a stable reference source for the fail-safe clock monitor. this option constantly monitors the main clock source against a reference signal provided by the internal oscillator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown.
pic24fj64ga004 family ds39881b-page 8 preliminary ? 2007 microchip technology inc. 1.1.4 easy migration regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. the consistent pinout scheme used throughout the entire family also aids in migrating to the next larger device. this is true when moving between devices with the same pin count, or even jumping from 28-pin to 44-pin devices. the pic24f family is pin-compatible with devices in the dspic33 family, and shares some compatibility with the pinout schema for pic18 and dspic30. this extends the ability of applications to grow from the relatively simple, to the powerful and complex, yet still selecting a microchip device. 1.2 other special features ? communications: the pic24fj64ga004 family incorporates a range of serial communication peripherals to handle a range of application requirements. there are two independent i 2 c modules that support both master and slave modes of operation. devices also have, through the peripheral pin select feature, two indepen- dent uarts with built-in irda encoder/decoders and two spi modules. ? peripheral pin select: the peripheral pin select feature allows most digital peripherals to be mapped over a fixed set of digital i/o pins. users may independently map the input and/or output of any one of the many digital peripherals to any one of the i/o pins. ? parallel master/enhanced parallel slave port: one of the general purpose i/o ports can be reconfigured for enhanced parallel data communi- cations. in this mode, the port can be configured for both master and slave operations, and supports 8-bit and 16-bit data transfers with up to 16 external address lines in master modes. ? real-time clock/calendar: this module implements a full-featured clock and calendar with alarm functions in hardware, freeing up timer resources and program memory space for use of the core application. ? 10-bit a/d converter: this module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, as well as faster sampling speeds. 1.3 details on individual family members devices in the pic24fj64ga004 family are available in 28-pin and 44-pin packages. the general block diagram for all devices is shown in figure 1-1. the devices are differentiated from each other in two ways: 1. flash program memory (64 kbytes for pic24fj64ga devices, 48 kbytes for pic24fj48ga devices, 32 kbytes for pic24fj32ga devices and 16 kbytes for pic24fj16ga devices). 2. internal sram memory (4k for pic24fj16ga devices, 8k for all other devices in the family). 3. available i/o pins and ports (21 pins on 2 ports for 28-pin devices and 35 pins on 3 ports for 44-pin devices). all other features for devices in this family are identical. these are summarized in table 1-1. a list of the pin features available on the pic24fj64ga004 family devices, sorted by function, is shown in table 1-2. note that this table shows the pin location of individual peripheral features and not how they are multiplexed on the same pin. this information is provided in the pinout diagrams in the beginning of the data sheet. multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first.
? 2007 microchip technology inc. preliminary ds39881b-page 9 pic24fj64ga004 family table 1-1: device features for the pic24fj64ga004 family features 16ga002 32ga002 48ga002 64ga002 16ga004 32ga004 48ga004 64ga004 operating frequency dc ? 32 mhz program memory (bytes) 16k 32k 48k 64k 16k 32k 48k 64k program memory (instructions) 5,504 11,008 16,512 22,016 5,504 11,008 16,512 22,016 data memory (bytes) 4096 8192 4096 8192 interrupt sources (soft vectors/nmi traps) 43 (39/4) i/o ports ports a, b ports a, b, c total i/o pins 21 35 timers: total number (16-bit) 5 (1) 32-bit (from paired 16-bit timers) 2 input capture channels 5 (1) output compare/pwm channels 5 (1) input change notification interrupt 21 30 serial communications: uart 2 (1) spi (3-wire/4-wire) 2 (1) i 2 c? 2 parallel communications (pmp/psp) yes jtag boundary scan yes 10-bit analog-to-digital module (input channels) 10 13 analog comparators 2 remappable pins 16 26 resets (and delays) por, bor, reset instruction, mclr , wdt; illegal opcode, repeat instruction hardware traps, configuration word mismatch (pwrt, ost, pll lock) instruction set 76 base instructions, multiple addressing mode variations packages 28-pin spdip/ssop/soic/qfn 44-pin qfn/tqfp note 1: peripherals are accessible through remappable pins.
pic24fj64ga004 family ds39881b-page 10 preliminary ? 2007 microchip technology inc. figure 1-1: pic24fj64ga004 family general block diagram instruction decode & control 16 pch pcl 16 program counter 16-bit alu 23 24 data bus inst register pcu 16 divide support inst latch 16 ea mux read agu write agu 16 16 8 interrupt controller psv & table data access control block stack control logic repeat control logic data latch data ram address latch address latch program memory data latch 16 address bus literal data 23 control signals 16 16 16 x 16 w reg array multiplier 17x17 osci/clki osco/clko v dd , timing generation v ss mclr power-up timer oscillator start-up timer power-on reset watchdog timer bor and precision reference band gap frc/lprc oscillators regulator voltage v ddcore /v cap disvreg porta (1) portc (1) ra0:ra9 rc0:rc9 portb rb0:rb15 note 1: not all pins or features are implemented on all device pinout configurations. see table 1-2 for i/o port pin descriptions. 2: bor functionality is provided when the on-board voltage regulator is enabled. 3: peripheral i/os are accessible through remappable pins. rp (1) rp0:rp25 comparators (3) timer2/3 (3) timer1 rtcc ic1-5 (3) adc 10-bit pwm/ spi1/2 (3) i2c1/2 timer4/5 (3) pmp/psp oc1-5 (3) cn1-22 (1) uart1/2 (3) lvd (2)
? 2007 microchip technology inc. preliminary ds39881b-page 11 pic24fj64ga004 family table 1-2: pic24fj64ga004 family pinout descriptions function pin number i/o input buffer description 28-pin spdip/ ssop/soic 28-pin qfn 44-pin qfn/tqfp an0 2 27 19 i ana a/d analog inputs. an1 3 28 20 i ana an2 4 1 21 i ana an3 5 2 22 i ana an4 6 3 23 i ana an5 7 4 24 i ana an6 ? ? 25 i ana an7 ? ? 26 i ana an8 ? ? 27 i ana an9 26 23 15 i ana an10 25 22 14 i ana an11 24 21 11 i ana an12 23 20 10 i ana av dd ? ? 17 p ? positive supply for analog modules. av ss ? ? 16 p ? ground reference for analog modules. c1in- 6 3 23 i ana comparator 1 negative input. c1in+ 7 4 24 i ana comparator 1 positive input. c2in- 4 1 21 i ana comparator 2 negative input. c2in+ 5 2 22 i ana comparator 2 positive input. clki 9 6 30 i ana main clock input connection. clko 10 7 31 o ? system clock output. legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note 1: alternative multiplexing for sda1 and scl1 when i2c1sel configuration bit is cleared.
pic24fj64ga004 family ds39881b-page 12 preliminary ? 2007 microchip technology inc. cn0 12 9 34 i st interrupt-on-change inputs. cn1 11 8 33 i st cn2 2 27 19 i st cn3 3 28 20 i st cn4 4 1 21 i st cn5 5 2 22 i st cn6 6 3 23 i st cn7 7 4 24 i st cn8 ? ? 25 i st cn9 ? ? 26 i st cn10 ? ? 27 i st cn11 26 23 15 i st cn12 25 22 14 i st cn13 24 21 11 i st cn14 23 20 10 i st cn15 22 19 9 i st cn16 21 18 8 i st cn17 ? ? 3 i st cn18 ? ? 2 i st cn19 ? ? 5 i st cn20 ? ? 4 i st cn21 18 15 1 i st cn22 17 14 44 i st cn23 16 13 43 i st cn24 15 12 42 i st cn25 ? ? 37 i st cn26 ? ? 38 i st cn27 14 11 41 i st cn28 ? ? 36 i st cn29 10 7 31 i st cn30 9 6 30 i st cv ref 25 22 14 o ana comparator voltage reference output. disvreg 19 16 6 i st voltage regulator disable. emuc1 5 2 21 i/o st in-circuit emulator clock input/output. emud1 4 1 22 i/o st in-circuit emulator data input/output. emuc2 22 19 9 i/o st in-circuit emulator clock input/output. emud2 21 18 8 i/o st in-circuit emulator data input/output. emuc3 15 12 42 i/o st in-circuit emulator clock input/output. emud3 14 11 41 i/o st in-circuit emulator data input/output. int0 16 13 43 i st external interrupt input. mclr 1 26 18 i st master clear (device rese t) input. this line is brought low to cause a reset. table 1-2: pic24fj64ga004 family pinout descriptions (continued) function pin number i/o input buffer description 28-pin spdip/ ssop/soic 28-pin qfn 44-pin qfn/tqfp legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note 1: alternative multiplexing for sda1 and scl1 when i2c1sel configuration bit is cleared.
? 2007 microchip technology inc. preliminary ds39881b-page 13 pic24fj64ga004 family osci 9 6 30 i ana main oscillator input connection. osco 10 7 31 o ana main oscillator output connection. pgc1 5 2 22 i/o st in-circuit debugger and icsp? programming clock pgd1 4 1 21 i/o st in-circuit debugger and icsp programming data. pgc2 22 19 9 i/o st in-circuit debugger and icsp programming clock. pgd2 21 18 8 i/o st in-circuit debugger and icsp programming data. pgc3 14 12 42 i/o st in-circuit debugger and icsp programming clock. pgd3 15 11 41 i/o st in-circuit debugger and icsp programming data. pma0 10 7 3 i/o st parallel master port address bit 0 input (buffered slave modes) and output (master modes). pma1 12 9 2 i/o st parallel master port address bit 1 input (buffered slave modes) and output (master modes). pma2 ? ? 27 o ? parallel master port address (demultiplexed master modes). pma3 ? ? 38 o ? pma4 ? ? 37 o ? pma5 ? ? 4 o ? pma6 ? ? 5 o ? pma7 ? ? 13 o ? pma8 ? ? 32 o ? pma9 ? ? 35 o ? pma10 ? ? 12 o ? pma11 ? ? ? o ? pma12 ? ? ? o ? pma13 ? ? ? o ? pmbe 11 8 36 o ? parallel master port byte enable strobe. pmcs1 26 23 15 o ? parallel master port chip select 1 strobe/address bit 14. pmd0 23 20 10 i/o st parallel master port data (demultiplexed master mode) or address/data (multiplexed master modes). pmd1 22 19 9 i/o st pmd2 21 18 8 i/o st pmd3 18 15 1 i/o st pmd4 17 14 44 i/o st pmd5 16 13 43 i/o st pmd6 15 12 42 i/o st pmd7 14 11 41 i/o st pmrd 24 21 11 o ? parallel master port read strobe. pmwr 25 22 14 o ? parallel master port write strobe. table 1-2: pic24fj64ga004 family pinout descriptions (continued) function pin number i/o input buffer description 28-pin spdip/ ssop/soic 28-pin qfn 44-pin qfn/tqfp legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note 1: alternative multiplexing for sda1 and scl1 when i2c1sel configuration bit is cleared.
pic24fj64ga004 family ds39881b-page 14 preliminary ? 2007 microchip technology inc. ra0 2 27 19 i/o st porta digital i/o. ra1 3 28 20 i/o st ra2 9 6 30 i/o st ra3 10 7 31 i/o st ra4 12 9 34 i/o st ra7 ? ? 13 i/o st ra8 ? ? 32 i/o st ra9 ? ? 35 i/o st ra10 ? ? 12 i/o st rb0 4 1 21 i/o st portb digital i/o. rb1 5 2 22 i/o st rb2 6 3 23 i/o st rb3 7 4 24 i/o st rb4 11 8 33 i/o st rb5 14 11 41 i/o st rb6 15 12 42 i/o st rb7 16 13 43 i/o st rb8 17 14 44 i/o st rb9 18 15 1 i/o st rb10 21 18 8 i/o st rb11 22 19 9 i/o st rb12 23 20 10 i/o st rb13 24 21 11 i/o st rb14 25 22 14 i/o st rb15 26 23 15 i/o st rc0 ? ? 25 i/o st portc digital i/o. rc1 ? ? 26 i/o st rc2 ? ? 27 i/o st rc3 ? ? 36 i/o st rc4 ? ? 37 i/o st rc5 ? ? 38 i/o st rc6 ? ? 2 i/o st rc7 ? ? 3 i/o st rc8 ? ? 4 i/o st rc9 ? ? 5 i/o st table 1-2: pic24fj64ga004 family pinout descriptions (continued) function pin number i/o input buffer description 28-pin spdip/ ssop/soic 28-pin qfn 44-pin qfn/tqfp legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note 1: alternative multiplexing for sda1 and scl1 when i2c1sel configuration bit is cleared.
? 2007 microchip technology inc. preliminary ds39881b-page 15 pic24fj64ga004 family rp0 4 1 21 i/o st remappable peripheral. rp1 5 2 22 i/o st rp2 6 3 23 i/o st rp3 7 4 24 i/o st rp4 11 8 33 i/o st rp5 14 11 41 i/o st rp6 15 12 42 i/o st rp7 16 13 43 i/o st rp8 17 14 44 i/o st rp9 18 15 1 i/o st rp10 21 18 8 i/o st rp11 22 19 9 i/o st rp12 23 20 10 i/o st rp13 24 21 11 i/o st rp14 25 22 14 i/o st rp15 26 23 15 i/o st rp16 ? ? 25 i/o st rp17 ? ? 26 i/o st rp18 ? ? 27 i/o st rp19 ? ? 36 i/o st rp20 ? ? 37 i/o st rp21 ? ? 38 i/o st rp22 ? ? 2 i/o st rp23 ? ? 3 i/o st rp24 ? ? 4 i/o st rp25 ? ? 5 i/o st rtcc 25 22 14 o ? real-time clock alarm output. scl1 17, 15 (1) 14, 12 (1) 44, 42 (1) i/o i 2 c i2c1 synchronous serial clock input/output. scl2 7 4 i/o i 2 c i2c2 synchronous serial clock input/output. sda1 18, 14 (1) 15, 11 (1) 1, 41 (1) i/o i 2 c i2c1 data input/output. sda2 6 3 i/o i 2 c i2c2 data input/output. sosci 11 8 33 i ana secondary oscillator/timer1 clock input. sosco 12 9 34 o ana secondary oscillator/timer1 clock output. table 1-2: pic24fj64ga004 family pinout descriptions (continued) function pin number i/o input buffer description 28-pin spdip/ ssop/soic 28-pin qfn 44-pin qfn/tqfp legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note 1: alternative multiplexing for sda1 and scl1 when i2c1sel configuration bit is cleared.
pic24fj64ga004 family ds39881b-page 16 preliminary ? 2007 microchip technology inc. t1ck 12 9 34 i st timer1 clock. tck 17 14 13 i st jtag test clock/programming clock input. tdi 21 18 35 i st jtag test data/programming data input. tdo 18 15 32 o ? jtag test data output. tms 22 19 12 i st jtag test mode select input. v dd 13, 28 10, 25 28, 40 p ? positive supply for peripheral digital logic and i/o pins. v ddcap 20 17 7 p ? external filter capacitor connection (regulator enabled). v ddcore 20 17 7 p ? positive supply for microcontroller core logic (regulator disabled). v ref - 3 28 20 i ana a/d and comparator reference voltage (low) input. v ref + 2 27 19 i ana a/d and comparator reference voltage (high) input. v ss 8, 27 5, 24 29, 39 p ? ground reference for logic and i/o pins. table 1-2: pic24fj64ga004 family pinout descriptions (continued) function pin number i/o input buffer description 28-pin spdip/ ssop/soic 28-pin qfn 44-pin qfn/tqfp legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note 1: alternative multiplexing for sda1 and scl1 when i2c1sel configuration bit is cleared.
? 2007 microchip technology inc. preliminary ds39881b-page 17 pic24fj64ga004 family 2.0 cpu the pic24f cpu has a 16-bit (data) modified harvard architecture with an enhanced instruction set and a 24-bit instruction word with a variable length opcode field. the program counter (pc) is 23 bits wide and addresses up to 4m instructions of user program memory space. a single-cycle instruction prefetch mechanism is used to help maintain throughput and pro- vides predictable execution. all instructions execute in a single cycle, with the exception of instructions that change the program flow, the double-word move ( mov.d ) instruction and the table instructions. over- head-free program loop constructs are supported using the repeat instructions, which are interruptible at any point. pic24f devices have sixteen, 16-bit working registers in the programmer?s model. each of the working registers can act as a data, address or address offset register. the 16th working register (w15) operates as a software stack pointer for interrupts and calls. the upper 32 kbytes of the data space memory map can optionally be mapped into program space at any 16k word boundary defined by the 8-bit program space visibility page address (psvpag) register. the program to data space mapping feature lets any instruction access program space as if it were data space. the instruction set architecture (isa) has been significantly enhanced beyond that of the pic18, but maintains an acceptable level of backward compatibil- ity. all pic18 instructions and addressing modes are supported, either directly, or through simple macros. many of the isa enhancements have been driven by compiler efficiency needs. the core supports inherent (no operand), relative, literal, memory direct and three groups of addressing modes. all modes support register direct and various register indirect modes. each group offers up to seven addressing modes. instructions are associated with predefined addressing modes depending upon their functional requirements. for most instructions, the core is capable of executing a data (or program data) memory read, a working reg- ister (data) read, a data memory write and a program (instruction) memory read per instruction cycle. as a result, three-parameter instructions can be supported, allowing trinary operations (that is, a + b = c) to be executed in a single cycle. a high-speed, 17-bit by 17-bit multiplier has been included to significantly enhance the core arithmetic capability and throughput. the multiplier supports signed, unsigned and mixed mode, 16-bit by 16-bit or 8-bit by 8-bit, integer multiplication. all multiply instructions execute in a single cycle. the 16-bit alu has been enhanced with integer divide assist hardware that supports an iterative non-restoring divide algorithm. it operates in conjunction with the repeat instruction looping mechanism and a selection of iterative divide instructions to support 32-bit (or 16-bit), divided by 16-bit, integer signed and unsigned division. all divide operations require 19 cycles to complete but are interruptible at any cycle boundary. the pic24f has a vectored exception scheme with up to 8 sources of non-maskable traps and up to 118 inter- rupt sources. each interrupt source can be assigned to one of seven priority levels. a block diagram of the cpu is shown in figure 2-1. 2.1 programmer?s model the programmer?s model for the pic24f is shown in figure 2-2. all registers in the programmer?s model are memory mapped and can be manipulated directly by instructions. a description of each register is provided in table 2-1. all registers associated with the programmer?s model are memory mapped. note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the associated ?pic24f family reference manual? chapter.
pic24fj64ga004 family ds39881b-page 18 preliminary ? 2007 microchip technology inc. figure 2-1: pic24f cp u core block diagram instruction decode & control pch pcl 16 program counter 16-bit alu 23 23 24 23 data bus instruction reg pcu 16 16 x 16 w register array divide support rom latch 16 ea mux ragu wagu 16 16 8 interrupt controller psv & table data access control block stack control logic loop control logic data latch data ram address latch control signals to various blocks program memory data latch address bus 16 literal data 16 16 hardware multiplier 16 to peripheral modules address latch
? 2007 microchip technology inc. preliminary ds39881b-page 19 pic24fj64ga004 family table 2-1: cpu core registers figure 2-2: programmer?s model register(s) name description w0 through w15 working register array pc 23-bit program counter sr alu status register splim stack pointer limit value register tblpag table memory page address register psvpag program space visibility page address register rcount repeat loop counter register corcon cpu control register novz c tblpag 22 0 7 0 0 15 program counter table memory page alu status register (sr) working/address registers w0 (wreg) w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12 w13 frame pointer stack pointer psvpag 7 0 program space visibility ra 0 rcount 15 0 repeat loop counter splim stack pointer limit srl registers or bits shadowed for push.s and pop.s instructions. 0 0 page address register 15 0 cpu control register (corcon) srh w14 w15 dc ipl 210 ?? ? ? ? ? ? ipl3 psv ???????????? ?? pc divider working registers multiplier registers 15 0 value register address register register
pic24fj64ga004 family ds39881b-page 20 preliminary ? 2007 microchip technology inc. 2.2 cpu control registers register 2-1: sr: alu status register u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w -0 ? ? ? ? ? ? ?dc bit 15 bit 8 r/w -0 (1) r/w -0 (1) r/w -0 (1) r-0 r/w -0 r/w -0 r/w -0 r/w -0 ipl2 (2) ipl1 (2) ipl0 (2) ra n ov z c bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-9 unimplemented: read as ? 0 ? bit 8 dc: alu half carry/borrow bit 1 = a carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = no carry-out from the 4th or 8th low-order bit of the result has occurred bit 7-5 ipl2:ipl0: cpu interrupt priority level status bits (1,2) 111 = cpu interrupt priority level is 7 (15); user interrupts disabled. 110 = cpu interrupt priority level is 6 (14) 101 = cpu interrupt priority level is 5 (13) 100 = cpu interrupt priority level is 4 (12) 011 = cpu interrupt priority level is 3 (11) 010 = cpu interrupt priority level is 2 (10) 001 = cpu interrupt priority level is 1 (9) 000 = cpu interrupt priority level is 0 (8) bit 4 ra: repeat loop active bit 1 = repeat loop in progress 0 = repeat loop not in progress bit 3 n: alu negative bit 1 = result was negative 0 = result was non-negative (zero or positive) bit 2 ov: alu overflow bit 1 = overflow occurred for signed (2?s complement) arithmetic in this arithmetic operation 0 = no overflow has occurred bit 1 z: alu zero bit 1 = an operation which effects the z bit has set it at some time in the past 0 = the most recent operation which effects the z bit has cleared it (i.e., a non-zero result) bit 0 c: alu carry/borrow bit 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note 1: the ipl status bits are read-only when nstdis (intcon1<15>) = 1 . 2: the ipl status bits are concatenated with the ipl3 bit (corcon<3>) to form the cpu interrupt priority level (ipl). the value in parentheses indicates the ipl when ipl3 = 1 .
? 2007 microchip technology inc. preliminary ds39881b-page 21 pic24fj64ga004 family 2.3 arithmetic logic unit (alu) the pic24f alu is 16 bits wide and is capable of addi- tion, subtraction, bit shifts and logic operations. unless otherwise mentioned, arithmetic operations are 2?s complement in nature. depending on the operation, the alu may affect the values of the carry (c), zero (z), negative (n), overflow (ov) and digit carry (dc) status bits in the sr register. the c and dc status bits operate as borrow and digit borrow bits, respectively, for subtraction operations. the alu can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. data for the alu operation can come from the w register array, or data memory, depending on the addressing mode of the instruction. likewise, output data from the alu can be written to the w register array or a data memory location. the pic24f cpu incorporates hardware support for both multiplication and division. this includes a dedi- cated hardware multiplier and support hardware for 16-bit divisor division. 2.3.1 multiplier the alu contains a high-speed, 17-bit x 17-bit multiplier. it supports unsigned, signed or mixed sign operation in several multiplication modes: 1. 16-bit x 16-bit signed 2. 16-bit x 16-bit unsigned 3. 16-bit signed x 5-bit (literal) unsigned 4. 16-bit unsigned x 16-bit unsigned 5. 16-bit unsigned x 5-bit (literal) unsigned 6. 16-bit unsigned x 16-bit signed 7. 8-bit unsigned x 8-bit unsigned register 2-2: corcon: cpu control register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 r/c-0 r/w -0 u-0 u-0 ? ? ? ?ipl3 (1) psv ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-4 unimplemented: read as ? 0 ? bit 3 ipl3: cpu interrupt priority level status bit (1) 1 = cpu interrupt priority level is greater than 7 0 = cpu interrupt priority level is 7 or less bit 2 psv: program space visibility in data space enable bit 1 = program space visible in data space 0 = program space not visible in data space bit 1-0 unimplemented: read as ? 0 ? note 1: user interrupts are disabled when ipl3 = 1 .
pic24fj64ga004 family ds39881b-page 22 preliminary ? 2007 microchip technology inc. 2.3.2 divider the divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: 1. 32-bit signed/16-bit signed divide 2. 32-bit unsigned/16-bit unsigned divide 3. 16-bit signed/16-bit signed divide 4. 16-bit unsigned/16-bit unsigned divide the quotient for all divide instructions ends up in w0 and the remainder in w1. sixteen-bit signed and unsigned div instructions can specify any w register for both the 16-bit divisor (wn), and any w register (aligned) pair (w(m + 1):wm) for the 32-bit dividend. the divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. 2.3.3 multi-bit shift support the pic24f alu supports both single bit and single-cycle, multi-bit arithmetic and logic shifts. multi-bit shifts are implemented using a shifter block, capable of performing up to a 15-bit arithmetic right shift, or up to a 15-bit left shift, in a single cycle. all multi-bit shift instructions only support register direct addressing for both the operand source and result destination. a full summary of instructions that use the shift operation is provided below in table 2-2. table 2-2: instructions that use the si ngle and multi-bit shift operation instruction description asr arithmetic shift right source register by one or more bits. sl shift left source register by one or more bits. lsr logical shift right source register by one or more bits.
? 2007 microchip technology inc. preliminary ds39881b-page 23 pic24fj64ga004 family 3.0 memory organization as harvard architecture devices, pic24f micro- controllers feature separate program and data memory spaces and busses. this architecture also allows the direct access of program memory from the data space during code execution. 3.1 program address space the program address memory space of pic24fj64ga004 family devices is 4m instructions. the space is addressable by a 24-bit value derived from either the 23-bit program counter (pc) during pro- gram execution, or from table operation or data space remapping, as described in section 3.3 ?interfacing program and data memory spaces? . user access to the program memory space is restricted to the lower half of the address range (000000h to 7fffffh). the exception is the use of tblrd/tblwt operations which use tblpag<7> to permit access to the configuration bits and device id sections of the configuration memory space. memory maps for the pic24fj64ga004 family of devices are shown in figure 3-1. figure 3-1: program space memory map for pic24fj64ga004 family devices 000000h 0000feh 000002h 000100h f8000eh f80010h fefffeh ffffffh 000004h 000200h 0001feh 000104h reset address user flash program memory (11k instructions) devid (2) goto instruction reserved alternate vector table reserved interrupt vector table pic24fj32ga configuration memory space user memory space flash config words note: memory areas are not shown to scale. reset address device config registers devid (2) goto instruction reserved alternate vector table reserved interrupt vector table pic24fj48ga ff0000h f7fffeh f80000h device config registers 800000h 7fffffh reserved reserved flash config words 00ac00h 00abfeh unimplemented read ? 0 ? unimplemented read ? 0 ? reset address device config registers user flash program memory (22k instructions) devid (2) goto instruction reserved alternate vector table reserved interrupt vector table pic24fj64ga reserved flash config words unimplemented read ? 0 ? reset address devid (2) goto instruction reserved alternate vector table reserved interrupt vector table pic24fj16ga flash config words device config registers reserved unimplemented read ? 0 ? 005800h 0057feh 002c00h 002bfeh user flash program memory (5.5k instructions) 008400h 0083feh user flash program memory (16k instructions)
pic24fj64ga004 family ds39881b-page 24 preliminary ? 2007 microchip technology inc. 3.1.1 program memory organization the program memory space is organized in word-addressable blocks. although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. the lower word always has an even address, while the upper word has an odd address (figure 3-2). program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during code execution. this arrangement also provides compatibility with data memory space addressing and makes it possible to access data in the program memory space. 3.1.2 hard memory vectors all pic24f devices reserve the addresses between 00000h and 000200h for hard coded program execu- tion vectors. a hardware reset vector is provided to redirect code execution from the default value of the pc on device reset to the actual start of code. a goto instruction is programmed by the user at 000000h, with the actual address for the start of code at 000002h. pic24f devices also have two interrupt vector tables, located from 000004h to 0000ffh and 000100h to 0001ffh. these vector tables allow each of the many device interrupt sources to be handled by separate isrs. a more detailed discussion of the interrupt vector tables is provided in section 6.1 ?interrupt vector table? . 3.1.3 flash configuration words in pic24fj64ga004 family devices, the top two words of on-chip program memory are reserved for configura- tion information. on device reset, the configuration information is copied into the appropriate configuration registers. the addresses of the flash configuration word for devices in the pic24fj64ga004 family are shown in table 3-1. their location in the memory map is shown with the other memory vectors in figure 3-1. the configuration words in program memory are a compact format. the actual configuration bits are mapped in several different regi sters in the configuration memory space. their order in the flash configuration words do not reflect a corresponding arrangement in the configuration space. additional details on the device configuration words are provided in section 23.1 ?configuration bits? . table 3-1: flash configuration words for pic24fj64ga004 family devices figure 3-2: program memory organization device program memory (k words) configuration word addresses pic24fj16ga 5.5 002bfch: 002bfeh pic24fj32ga 11 0057fch: 0057feh pic24fj48ga 16 0083fch: 0083feh pic24fj64ga 22 00abfch: 00abfeh 0 8 16 pc address 000000h 000002h 000004h 000006h 23 00000000 00000000 00000000 00000000 program memory ?phantom? byte (read as ? 0 ?) least significant word most significant word instruction width 000001h 000003h 000005h 000007h msw address (lsw address)
? 2007 microchip technology inc. preliminary ds39881b-page 25 pic24fj64ga004 family 3.2 data address space the pic24f core has a separate, 16-bit wide data mem- ory space, addressable as a single linear range. the data space is accessed using two address generation units (agus), one each for read and write operations. the data space memory map is shown in figure 3-3. all effective addresses (eas) in the data memory space are 16 bits wide and point to bytes within the data space. this gives a data space address range of 64 kbytes or 32k words. the lower half of the data memory space (that is, when ea<15> = 0 ) is used for implemented memory addresses, while the upper half (ea<15> = 1 ) is reserved for the program space visibility area (see section 3.3.3 ?reading data from program memory using program space visibility? ). pic24fj64ga family devices implement a total of 8 kbytes of data memory. should an ea point to a location outside of this area, an all zero word or byte will be returned. 3.2.1 data space width the data memory space is organized in byte-addressable, 16-bit wide blocks. data is aligned in data memory and registers as 16-bit words, but all data space eas resolve to bytes. the least significant bytes of each word have even addresses, while the most significant bytes have odd addresses. figure 3-3: data space memory map fo r pic24fj64ga004 family devices (1) 0000h 07feh fffeh lsb address lsb msb msb address 0001h 07ffh 1fffh ffffh 8001h 8000h 7fffh 0801h 0800h 2001h near 1ffeh sfr sfr space data ram 2000h 7fffh program space visibility area note 1: data memory areas are not shown to scale. 2: upper memory limit for pic24fj16gaxxx devices is 17ffh. 27feh (2) 2800h 27ffh (2) 2801h space data space implemented data ram unimplemented read as ? 0 ?
pic24fj64ga004 family ds39881b-page 26 preliminary ? 2007 microchip technology inc. 3.2.2 data memory organization and alignment to maintain backward compatibility with pic ? devices and improve data space memory usage efficiency, the pic24f instruction set supports both word and byte operations. as a consequence of byte accessibility, all effective address calculations are internally scaled to step through word-aligned memory. for example, the core recognizes that post-modified register indirect addressing mode [ws++] will result in a value of ws + 1 for byte operations and ws + 2 for word operations. data byte reads will read the complete word which con- tains the byte, using the lsb of any ea to determine which byte to select. the selected byte is placed onto the lsb of the data path. that is, data memory and reg- isters are organized as two parallel, byte-wide entities with shared (word) address decode but separate write lines. data byte writes only write to the corresponding side of the array or register which matches the byte address. all word accesses must be aligned to an even address. misaligned word data fetches are not supported, so care must be taken when mixing byte and word opera- tions, or translating from 8-bit mcu code. if a misaligned read or write is attempted, an address error trap will be generated. if the error occurred on a read, the instruction underway is completed; if it occurred on a write, the instruction will be executed but the write will not occur. in either case, a trap is then executed, allow- ing the system and/or user to examine the machine state prior to execution of the address fault. all byte loads into any w register are loaded into the least significant byte. the most significant byte is not modified. a sign-extend instruction ( se ) is provided to allow users to translate 8-bit signed data to 16-bit signed values. alternatively, for 16-bit unsigned data, users can clear the msb of any w register by executing a zero-extend ( ze ) instruction on the appropriate address. although most instructions are capable of operating on word or byte data sizes, it should be noted that some instructions operate only on words. 3.2.3 near data space the 8-kbyte area between 0000h and 1fffh is referred to as the near data space. locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. the remainder of the data space is addressable indirectly. additionally, the whole data space is addressable using mov instructions, which support memory direct addressing with a 16-bit address field. 3.2.4 sfr space the first 2 kbytes of the near data space, from 0000h to 07ffh, are primarily occupied with special function registers (sfrs). these are used by the pic24f core and peripheral modules for controlling the operation of the device. sfrs are distributed among the modules that they con- trol and are generally grouped together by module. much of the sfr space contains unused addresses; these are read as ? 0 ?. a diagram of the sfr space, showing where sfrs are actually implemented, is shown in table 3-2. each implemented area indicates a 32-byte region where at least one address is imple- mented as an sfr. a complete listing of implemented sfrs, including their addresses, is shown in tables 3-3 through 3-24. table 3-2: implemented regions of sfr data space sfr space address xx00 xx20 xx40 xx60 xx80 xxa0 xxc0 xxe0 000h core icn interrupts ? 100h timers capture ? compare ? ? ? 200h i 2 c? uart spi ? ? i/o 300h a/d ? ? ? ? ? ? 400h ? ? ? ? ? ? ? ? 500h ? ? ? ? ? ? ? ? 600h pmp rtc/comp crc ? pps 700h ? ? system nvm/pmd ? ? ? ? legend: ? = no implemented sfrs in this block
? 2007 microchip technology inc. preliminary ds39881b-page 27 pic24fj64ga004 family table 3-3: cpu core registers map file name addrbit 15bit 14bit 13bit 12bit 11bit 10bit 9bit 8bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 all resets wreg0 0000 working register 0 0000 wreg1 0002 working register 1 0000 wreg2 0004 working register 2 0000 wreg3 0006 working register 3 0000 wreg4 0008 working register 4 0000 wreg5 000a working register 5 0000 wreg6 000c working register 6 0000 wreg7 000e working register 7 0000 wreg8 0010 working register 8 0000 wreg9 0012 working register 9 0000 wreg10 0014 working register 10 0000 wreg11 0016 working register 11 0000 wreg12 0018 working register 12 0000 wreg13 001a working register 13 0000 wreg14 001c working register 14 0000 wreg15 001e working register 15 0800 splim 0020 stack pointer limit value register xxxx pcl 002e program counter low byte register 0000 pch 0030 ? ? ? ? ? ? ? ? program counter high byte register 0000 tblpag 0032 ? ? ? ? ? ? ? ? table memory page address register 0000 psvpag 0034 ? ? ? ? ? ? ? ? program space visibility page address register 0000 rcount 0036 repeat loop counter register xxxx sr 0042 ? ? ? ? ? ? ? dc ipl2 ipl1 ipl0 ra n ov z c 0000 corcon 0044 ? ? ? ? ? ? ? ? ? ? ? ? ipl3 psv ? ? 0000 disicnt 0052 ? ? disable interrupts counter register xxxx legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 3-4: icn register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets cnen1 0060 cn15ie cn14ie cn13ie cn12ie cn11ie cn10ie (1) cn9ie (1) cn8ie (1) cn7ie cn6ie cn5ie cn4ie cn3ie cn2ie cn1ie cn0ie 0000 cnen2 0062 ? cn30ie cn29ie cn28ie (1) cn27ie cn26ie (1) cn25ie (1) cn24ie cn23ie cn22ie cn21ie cn20ie (1) cn19ie (1) cn18ie (1) cn17ie (1) cn16ie 0000 cnpu1 0068 cn15pue cn14pue cn13pue cn12pue cn11pue cn10pue (1) cn9pue (1) cn8pue (1) cn7pue cn6pue cn5pue cn4pue cn3pue cn2pue cn1pue cn0pue 0000 cnpu2 006a ? cn30pue cn29pue cn28pue (1) cn27pue cn26pue (1) cn25pue (1) cn24pue cn23pue cn22pue cn21pue cn20pue (1) cn19pue (1) cn18pue (1) cn17pue (1) cn16pue 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: bits not available on 28-pin devices; read as ? 0 ?.
pic24fj64ga004 family ds39881b-page 28 preliminary ? 2007 microchip technology inc. table 3-5: interrupt controller register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets intcon1 0080 nstdis ? ? ? ? ? ? ? ? ? ? matherr addrerr stkerr oscfail ? 0000 intcon2 0082 altivt disi ? ? ? ? ? ? ? ? ? ? ? int2ep int1ep int0ep 0000 ifs0 0084 ? ? ad1if u1txif u1rxif spi1if spf1if t3if t2if oc2if ic2if ? t1if oc1if ic1if int0if 0000 ifs1 0086 u2txif u2rxif int2if t5if t4if oc4if oc3if ? ? ? ? int1if cnif cmif mi2c1if si2c1if 0000 ifs2 0088 ? ?pmpif ? ? ?oc5if ? ic5if ic4if ic3if ? ? ? spi2if spf2if 0000 ifs3 008a ?rtcif ? ? ? ? ? ? ? ? ? ? ?mi2c2ifsi2c2if ? 0000 ifs4 008c ? ? ? ? ? ? ?lvdif ? ? ? ? crcif u2erif u1erif ? 0000 iec0 0094 ? ? ad1ie u1txie u1rxie spi1ie spf1ie t3ie t2ie oc2ie ic2ie ? t1ie oc1ie ic1ie int0ie 0000 iec1 0096 u2txie u2rxie int2ie t5ie t4ie oc4ie oc3ie ? ? ? ? int1ie cnie cmie mi2c1ie si2c1ie 0000 iec2 0098 ? ?pmpie ? ? ?oc5ie ? ic5ie ic4ie ic3ie ? ? ? spi2ie spf2ie 0000 iec3 009a ?rtcie ? ? ? ? ? ? ? ? ? ? ? mi2c2ie si2c2ie ? 0000 iec4 009c ? ? ? ? ? ? ?lvdie ? ? ? ? crcie u2erie u1erie ? 0000 ipc0 00a4 ? t1ip2 t1ip1 t1ip0 ? oc1ip2 oc1ip1 oc1ip0 ? ic1ip2 ic1ip1 ic1ip0 ? int0ip2 int0ip1 int0ip0 4444 ipc1 00a6 ? t2ip2 t2ip1 t2ip0 ? oc2ip2 oc2ip1 oc2ip0 ? ic2ip2 ic2ip1 ic2ip0 ? ? ? ? 4444 ipc2 00a8 ? u1rxip2 u1rxip1 u1rxip0 ? spi1ip2 spi1ip1 spi1ip0 ? spf1ip2 spf1ip1 spf1ip0 ? t3ip2 t3ip1 t3ip0 4444 ipc3 00aa ? ? ? ? ? ? ? ? ? ad1ip2 ad1ip1 ad1ip0 ? u1txip2 u1txip1 u1txip0 4444 ipc4 00ac ? cnip2 cnip1 cnip0 ? cmip2 cmip1 cmip0 ? mi2c1p2 mi2c1p1 mi2c1p0 ? si2c1p2 si2c1p1 si2c1p0 4444 ipc5 00ae ? ? ? ? ? ? ? ? ? ? ? ? ? int1ip2 int1ip1 int1ip0 4444 ipc6 00b0 ? t4ip2 t4ip1 t4ip0 ? oc4ip2 oc4ip1 oc4ip0 ? oc3ip2 oc3ip1 oc3ip0 ? ? ? ? 4444 ipc7 00b2 ? u2txip2 u2txip1 u2txip0 ? u2rxip2 u2rxip1 u2rxip0 ? int2ip2 int2ip1 int2ip0 ? t5ip2 t5ip1 t5ip0 4444 ipc8 00b4 ? ? ? ? ? ? ? ? ? spi2ip2 spi2ip1 spi2ip0 ? spf2ip2 spf2ip1 spf2ip0 4444 ipc9 00b6 ? ic5ip2 ic5ip1 ic5ip0 ? ic4ip2 ic4ip1 ic4ip0 ? ic3ip2 ic3ip1 ic3ip0 ? ? ? ? 4444 ipc10 00b8 ? ? ? ? ? ? ? ? ? oc5ip2 oc5ip1 oc5ip0 ? ? ? ? 4444 ipc11 00ba ? ? ? ? ? ? ? ? ? pmpip2 pmpip1 pmpip0 ? ? ? ? 4444 ipc12 00bc ? ? ? ? ? mi2c2p2 mi2c2p1 mi2c2p0 ? si2c2p2 si2c2p1 si2c2p0 ? ? ? ? 4444 ipc15 00c2 ? ? ? ? ? rtcip2rtcip1rtcip0 ? ? ? ? ? ? ? ? 4444 ipc16 00c4 ? crcip2 crcip1 crcip0 ? u2erip2 u2erip1 u2erip0 ? u1erip2 u1erip1 u1erip0 ? ? ? ? 4444 ipc18 00c8 ? ? ? ? ? ? ? ? ? ? ? ? ? lvdip2 lvdip1 lvdip0 4444 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
? 2007 microchip technology inc. preliminary ds39881b-page 29 pic24fj64ga004 family table 3-6: timer register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets tmr1 0100 timer1 register 0000 pr1 0102 timer1 period register ffff t1con 0104 ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 ? tsync tcs ? 0000 tmr2 0106 timer2 register 0000 tmr3h 0108 timer3 holding register (for 32-bit timer operations only) 0000 tmr3 010a timer3 register 0000 pr2 010c timer2 period register ffff pr3 010e timer3 period register ffff t2con 0110 ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 t32 ?tcs ? 0000 t3con 0112 ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 ? ?tcs ? 0000 tmr4 0114 timer4 register 0000 tmr5h 0116 timer5 holding register (for 32-bit operations only) 0000 tmr5 0118 timer5 register 0000 pr4 011a timer4 period register ffff pr5 011c timer5 period register ffff t4con 011e ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 t32 ?tcs ? 0000 t5con 0120 ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 ? ?tcs ? 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 3-7: input capture register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets ic1buf 0140 input 1 capture register ffff ic1con 0142 ? ?icsidl ? ? ? ? ? ictmr ici1 ici0 icov icbne icm2 icm1 icm0 0000 ic2buf 0144 input 2 capture register ffff ic2con 0146 ? ?icsidl ? ? ? ? ? ictmr ici1 ici0 icov icbne icm2 icm1 icm0 0000 ic3buf 0148 input 3 capture register ffff ic3con 014a ? ?icsidl ? ? ? ? ? ictmr ici1 ici0 icov icbne icm2 icm1 icm0 0000 ic4buf 014c input 4 capture register ffff ic4con 014e ? ?icsidl ? ? ? ? ? ictmr ici1 ici0 icov icbne icm2 icm1 icm0 0000 ic5buf 0150 input 5 capture register ffff ic5con 0152 ? ?icsidl ? ? ? ? ? ictmr ici1 ici0 icov icbne icm2 icm1 icm0 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
pic24fj64ga004 family ds39881b-page 30 preliminary ? 2007 microchip technology inc. table 3-8: output compare register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets oc1rs 0180 output compare 1 secondary register ffff oc1r 0182 output compare 1 register ffff oc1con 0184 ? ?ocsidl ? ? ? ? ? ? ? ? ocflt octsel ocm2 ocm1 ocm0 0000 oc2rs 0186 output compare 2 secondary register ffff oc2r 0188 output compare 2 register ffff oc2con 018a ? ?ocsidl ? ? ? ? ? ? ? ? ocflt octsel ocm2 ocm1 ocm0 0000 oc3rs 018c output compare 3 secondary register ffff oc3r 018e output compare 3 register ffff oc3con 0190 ? ?ocsidl ? ? ? ? ? ? ? ? ocflt octsel ocm2 ocm1 ocm0 0000 oc4rs 0192 output compare 4 secondary register ffff oc4r 0194 output compare 4 register ffff oc4con 0196 ? ?ocsidl ? ? ? ? ? ? ? ? ocflt octsel ocm2 ocm1 ocm0 0000 oc5rs 0198 output compare 5 secondary register ffff oc5r 019a output compare 5 register ffff oc5con 019c ? ?ocsidl ? ? ? ? ? ? ? ? ocflt octsel ocm2 ocm1 ocm0 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 3-9: i 2 c? register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets i2c1rcv 0200 ? ? ? ? ? ? ? ? receive register 1 0000 i2c1trn 0202 ? ? ? ? ? ? ? ? transmit register 1 00ff i2c1brg 0204 ? ? ? ? ? ? ? baud rate generator register 1 0000 i2c1con 0206 i2cen ? i2csidl sclrel ipmien a10m disslw smen gcen stren akdt acken rcen pen rsen sen 1000 i2c1stat 0208 akstat trstat ? ? ? bcl gcstat add10 iwcol i2cov d/a psr/w rbf tbf 0000 i2c1add 020a ? ? ? ? ? ? address register 1 0000 i2c1msk 020c ? ? ? ? ? ? amsk9 amsk8 amsk7 amsk6 amsk5 amsk4 amsk3 amsk2 amsk1 amsk? 0000 i2c2rcv 0210 ? ? ? ? ? ? ? ? receive register 2 0000 i2c2trn 0212 ? ? ? ? ? ? ? ? transmit register 2 00ff i2c2brg 0214 ? ? ? ? ? ? ? baud rate generator register 2 0000 i2c2con 0216 i2cen ? i2csidl sclrel ipmien a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 1000 i2c2stat 0218 ackstat trstat ? ? ? bcl gcstat add10 iwcol i2cov d/a psr/w rbf tbf 0000 i2c2add 021a ? ? ? ? ? ? address register 2 0000 i2c2msk 021c ? ? ? ? ? ? amsk9 amsk8 amsk7 amsk6 amsk5 amsk4 amsk3 amsk2 amsk1 amsk? 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
? 2007 microchip technology inc. preliminary ds39881b-page 31 pic24fj64ga004 family table 3-10: uart register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets u1mode 0220 uarten ? usidl iren rtsmd ? uen1 uen0 wake lpback abaud rxinv brgh pdsel1 pdsel0 stsel 0000 u1sta 0222 utxisel1 utxinv utxisel0 ? utxbrk utxen utxbf trmt urxisel1 urxisel0 adden ridle perr ferr oerr urxda 0110 u1txreg 0224 ? ? ? ? ? ? ? utx8 utx7 utx6 utx5 utx4 utx3 utx2 utx1 utx0 0000 u1rxreg 0226 ? ? ? ? ? ? ? urx8 urx7 urx6 urx5 urx4 urx3 urx2 urx1 urx0 0000 u1brg 0228 baud rate generator prescaler register 0000 u2mode 0230 uarten ? usidl iren rtsmd ? uen1 uen0 wake lpback abaud rxinv brgh pdsel1 pdsel0 stsel 0000 u2sta 0232 utxisel1 utxinv utxisel0 ? utxbrk utxen utxbf trmt urcisel1 urcisel0 adden ridle perr ferr oerr urxda 0110 u2txreg 0234 ? ? ? ? ? ? ? utx8 utx7 utx6 utx5 utx4 utx3 utx2 utx1 utx0 0000 u2rxreg 0236 ? ? ? ? ? ? ? urx8 urx7 urx6 urx5 urx4 urx3 urx2 urx1 urx0 0000 u2brg 0238 baud rate generator prescaler 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 3-11: spi register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets spi1stat 0240 spien ? spisidl ? ? spibec2 spibec1 spibec0 ? spirov ? ? ? ? spitbf spirbf 0000 spi1con1 0242 ? ? ? dissck dissdo mode16 smp cke ssen ckp msten spre2 spre1 spre0 ppre1 ppre0 0000 spi1con2 0244 frmen spifsd spifpol ? ? ? ? ? ? ? ? ? ? ? spife spiben 0000 spi1buf 0248 spi1 transmit/receive buffer 0000 spi2stat 0260 spien ? spisidl ? ? spibec2 spibec1 spibec0 ? spirov ? ? ? ? spitbf spirbf 0000 spi2con1 0262 ? ? ? dissck dissdo mode16 smp cke ssen ckp msten spre2 spre1 spre0 ppre1 ppre0 0000 spi2con2 0264 frmen spifsd spifpol ? ? ? ? ? ? ? ? ? ? ? spife spiben 0000 spi2buf 0268 spi2 transmit/receive buffer 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
pic24fj64ga004 family ds39881b-page 32 preliminary ? 2007 microchip technology inc. table 3-12: porta register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisa 02c0 ? ? ? ? ? trisa10 (1) trisa9 (1) trisa8 (1) trisa7 (1) ? ? trisa4 trisa3 (2) trisa2 (3) trisa1 trisa0 079f porta 02c2 ? ? ? ? ?ra10 (1) ra9 (1) ra8 (1) ra7 (1) ? ?ra4ra3 (2) ra2 (3) ra1 ra0 0000 lata 02c4 ? ? ? ? ?lata10 (1) lata9 (1) lata8 (1) lata7 (1) ? ?lata4lata3 (2) lata2 (3) lata1 lata0 0000 odca 02c6 ? ? ? ? ?oda10 (1) oda9 (1) oda8 (1) oda7 (1) ? ? oda4 oda3 (2) oda2 (3) oda1 oda0 0000 legend: ? = unimplemented, read as ? 0 ?. note 1: bits are not available on 28-pin devices; read as ? 0 ?. 2: bits are available only when the primary oscillator is disabled (poscmd<1:0> = 00 ); otherwise read as ? 0 ?. 3: bits are available only when the primary oscillator is disabled or ec mode is selected (poscmd<1:0> = 00 or 11 ) and clko is disabled (osciofnc = 0 ); otherwise, read as ? 0 ?. table 3-13: portb register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisb 02c8 trisb15 trisb14 trisb13 trisb12 trisb11 trisb10 trisb9 tr isb8 trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 ffff portb 02ca rb15 rb14 rb13 rb12 rb11 rb10 rb9 rb8 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 0000 latb 02cc latb15 latb14 latb13 latb12 latb11 latb10 latb9 latb8 latb7 latb6 latb5 latb4 latb3 latb2 latb1 latb0 0000 odcb 02ce odb15 odb14 odb13 odb12 odb11 odb10 odb9 odb8 odb7 odb6 odb5 odb4 odb3 odb2 odb1 odb0 0000 legend: ? = unimplemented, read as ? 0 ? table 3-14: portc register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisc (1) 02d0 ? ? ? ? ? ? trisc9 trisc8 trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 03ff portc (1) 02d2 ? ? ? ? ? ? rc9 rc8 rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 0000 latc (1) 02d4 ? ? ? ? ? ? latc9 latc8 latc7 latc6 latc5 latc4 latc3 latc2 latc1 latc0 0000 odcc (1) 02d6 ? ? ? ? ? ? odc9 osc8 odc7 odc6 odc5 odc4 odc3 odc2 odc1 odc0 0000 legend: ? = unimplemented, read as ? 0 ? note 1: bits not available on 28-pin devices; read as ? 0 ?. table 3-15: pad configuration register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets padcfg1 02fc ? ? ? ? ? ? ? ? ? ? ? ? ? ? rtsecsel pmpttl 0000 legend: ? = unimplemented, read as ? 0 ?
? 2007 microchip technology inc. preliminary ds39881b-page 33 pic24fj64ga004 family table 3-16: adc register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets ad1buf0 0300 adc data buffer 0 xxxx ad1buf1 0302 adc data buffer 1 xxxx ad1buf2 0304 adc data buffer 2 xxxx ad1buf3 0306 adc data buffer 3 xxxx ad1buf4 0308 adc data buffer 4 xxxx ad1buf5 030a adc data buffer 5 xxxx ad1buf6 030c adc data buffer 6 xxxx ad1buf7 030e adc data buffer 7 xxxx ad1buf8 0310 adc data buffer 8 xxxx ad1buf9 0312 adc data buffer 9 xxxx ad1bufa 0314 adc data buffer 10 xxxx ad1bufb 0316 adc data buffer 11 xxxx ad1bufc 0318 adc data buffer 12 xxxx ad1bufd 031a adc data buffer 13 xxxx ad1bufe 031c adc data buffer 14 xxxx ad1buff 031e adc data buffer 15 xxxx ad1con1 0320 adon ?adsidl ? ? ? form1 form0 ssrc2 ssrc1 ssrc0 ? ? asam samp done 0000 ad1con2 0322 vcfg2 vcfg1 vcfg0 ? ? cscna ? ?bufs ? smpi3 smpi2 smpi1 smpi0 bufm alts 0000 ad1con3 0324 adrc ? ? samc4 samc3 samc2 samc1 samc0 adcs7 adcs6 adcs5 adcs4 adcs3 adcs2 adcs1 adcs0 0000 ad1chs0 0328 ch0nb ? ? ? ch0sb3 ch0sb2 ch0sb1 ch0sb0 ch0na ? ? ? ch0sa3 ch0sa2 ch0sa1 ch0sa0 0000 ad1pcfg 032c ? ? ? pcfg12 pcfg11 pcfg10 pcfg9 pcfg8 pcfg7 pcfg6 pcfg5 pcfg4 pcfg3 pcfg2 pcfg1 pcfg0 0000 ad1cssl 0330 ? ? ? cssl12 cssl11 cssl10 cssl9 cssl8 cssl7 cssl6 cssl5 cssl4 cssl3 cssl2 cssl1 cssl0 0000 legend: ? = unimplemented, read as ? 0 ? table 3-17: parallel master/slave port register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pmcon 0600 pmpen ? psidl adrmux1 adrmux0 ptbeen ptwren ptrden csf1 csf0 alp ? cs1p bep wrsp rdsp 0000 pmmode 0602 busy irqm1 irqm0 incm1 incm0 mode16 mode1 mode0 waitb1 waitb0 waitm3 waitm2 waitm1 waitm0 waite1 waite0 0000 pmaddr 0604 ?cs1 ? ? ? addr10 addr9 addr8 addr7 addr6 addr5 addr4 addr3 addr2 addr1 addr0 0000 pmdout1 parallel port data out register 1 (buffers 0 and 1) 0000 pmdout2 0606 parallel port data out register 2 (buffers 2 and 3) 0000 pmdin1 0608 parallel port data in register 1 (buffers 0 and 1) 0000 pmdin2 060a parallel port data in register 2 (buffers 2 and 3) 0000 pmaen 060c ?pten14 ? ? ? pten10 pten9 pten8 pten7 pten6 pten5 pten4 pten3 pten2 pten1 pten0 0000 pmstat 060e ibf ibov ? ? ib3f ib2f ib1f ib0f obe obuf ? ? ob3e ob2e ob1e ob0e 0000 legend: ? = unimplemented, read as ? 0 ?.
pic24fj64ga004 family ds39881b-page 34 preliminary ? 2007 microchip technology inc. table 3-18: real-time clock and calendar register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets alrmval 0620 alarm value register window based on aptr<1:0> xxxx alcfgrpt 0622 alrmen chime amask3 amask2 amask1 amask0 alrmptr1 alrmptr0 arpt7 arpt6 arpt5 arpt4 arpt3 arpt2 arpt1 arpt0 0000 rtcval 0624 rtcc value register window based on rtcptr<1:0> xxxx rcfgcal 0626 rtcen ? rtcwren rtcsync halfsec rtcoe rtcptr1 rtcptr0 cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 0000 legend: ? = unimplemented, read as ? 0 ? table 3-19: dual comparator register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets cmcon 0630 cmidl ? c2evt c1evt c2en c1en c2outen c1outen c2out c1out c2inv c1inv c2neg c2pos c1neg c1pos 0000 cvrcon 0632 ? ? ? ? ? ? ? ? cvren cvroe cvrr cvrss cvr3 cvr2 cvr1 cvr0 0000 legend: ? = unimplemented, read as ? 0 ? table 3-20: crc register map file nameaddrbit 15bit 14bit 13bit 12bit 11bit 10bit 9bit 8bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 all resets crccon 0640 ? ? csidl vword4 vword3 vwo rd2 vword1 vword0 crcful crcmpt ? crcgo plen3 plen2 plen1 plen0 0040 crcxor0642x15x14x13x12x11x10x9x8x7x6x5x4x3x2x1 ? 0000 crcdat 0644 crc data input register 0000 crcwdat 0646 crc result register 0000 legend: ? = unimplemented, read as ? 0 ?
? 2007 microchip technology inc. preliminary ds39881b-page 35 pic24fj64ga004 family table 3-21: peripheral pin select register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rpinr0 0680 ? ? ? intr4 intr3 intr2 intr1 intr0 ? ? ? ? ? ? ? ? 1f00 rpinr1 0682 ? ? ? ? ? ? ? ? ? ? ? intr4 intr3 intr2 intr1 intr0 001f rpinr3 0686 ? ? ? t3ckr4 t3ckr3 t3ckr2 t3ckr1 t3ckr0 ? ? ? t2ckr4 t2ckr3 t2ckr2 t2ckr1 t2ckr0 1f1f rpinr4 0688 ? ? ? t5ckr4 t5ckr3 t5ckr2 t5ckr1 t5ckr0 ? ? ? t4ckr4 t4ckr3 t4ckr2 t4ckr1 t4ckr0 1f1f rpinr7 068e ? ? ? ic2r4 ic2r3 ic2r2 ic2r1 ic2r0 ? ? ? ic1r4 ic1r3 ic1r2 ic1r1 ic1r0 1f1f rpinr8 0690 ? ? ? ic4r4 ic4r3 ic4r2 ic4r1 ic4r0 ? ? ? ic3r4 ic3r3 ic3r2 ic3r1 ic3r0 1f1f rpinr9 0692 ? ? ? ? ? ? ? ? ? ? ? ic5r4 ic5r3 ic5r2 ic5r1 ic5r0 001f rpinr11 0696 ? ? ? ocfbr4 ocfbr3 ocfbr2 ocfbr1 ocfbr0 ? ? ? ocfar4 ocfar3 ocfar2 ocfar1 ocfar0 1f1f rpinr18 06a4 ? ? ? u1ctsr4 u1ctsr3 u1ctsr2 u1ctsr1 u1ctsr0 ? ? ? u1rxr4 u1rxr3 u1rxr2 u1rxr1 u1rxr0 1f1f rpinr19 06a6 ? ? ? u2ctsr4 u2ctsr3 u2ctsr2 u2ctsr1 u2ctsr0 ? ? ? u2rxr4 u2rxr3 u2rxr2 u2rxr1 u2rxr0 1f1f rpinr20 06a8 ? ? ? sck1r4 sck1r3 sck1r2 sck1r1 sck1r0 ? ? ? sdi1r4 sdi1r3 sdi1r2 sdi1r1 sdi1r0 1f1f rpinr21 06aa ? ? ? ? ? ? ? ? ? ? ? ss1r4 ss1r3 ss1r2 ss1r1 ss1r0 001f rpinr22 06ac ? ? ? sck2r4 sck2r3 sck2r2 sck2r1 sck2r0 ? ? ? sdi2r4 sdi2r3 sdi2r2 sdi2r1 sdi2r0 1f1f rpinr23 06ae ? ? ? ? ? ? ? ? ? ? ? ss2r4 ss2r3 ss2r2 ss2r1 ss2r0 001f rpor0 06c0 ? ? ? rp1r4 rp1r3 rp1r2 rp1r1 rp1r0 ? ? ? rp0r4 rp0r3 rp0r2 rp0r1 rp0r0 0000 rpor1 06c2 ? ? ? rp3r4 rp3r3 rp3r2 rp3r1 rp3r0 ? ? ? rp2r4 rp2r3 rp2r2 rp2r1 rp2r0 0000 rpor2 06c4 ? ? ? rp5r4 rp5r3 rp5r2 rp5r1 rp5r0 ? ? ? rp4r4 rp4r3 rp4r2 rp4r1 rp4r0 0000 rpor3 06c6 ? ? ? rp7r4 rp7r3 rp7r2 rp7r1 rp7r0 ? ? ? rp6r4 rp6r3 rp6r2 rp6r1 rp6r0 0000 rpor4 06c8 ? ? ? rp9r4 rp9r3 rp9r2 rp9r1 rp9r0 ? ? ? rp8r4 rp8r3 rp8r2 rp8r1 rp8r0 0000 rpor5 06ca ? ? ? rp11r4 rp11r3 rp11r2 rp11r1 rp11r0 ? ? ? rp10r4 rp10r3 rp10r2 rp10r1 rp10r0 0000 rpor6 06cc ? ? ? rp13r4 rp13r3 rp13r2 rp13r1 rp13r0 ? ? ? rp12r4 rp12r3 rp12r2 rp12r1 rp12r0 0000 rpor7 06ce ? ? ? rp15r4 rp15r3 rp15r2 rp15r1 rp15r0 ? ? ? rp14r4 rp14r3 rp14r2 rp14r1 rp14r0 0000 rpor8 06d0 ? ? ?rp17r4 (1) rp17r3 (1) rp17r2 (1) rp17r1 (1) rp17r0 (1) ? ? ?rp16r4 (1) rp16r3 (1) rp16r2 (1) rp16r1 (1) rp16r0 (1) 0000 rpor9 06d2 ? ? ?rp19r4 (1) rp19r3 (1) rp19r2 (1) rp19r1 (1) rp19r0 (1) ? ? ?rp18r4 (1) rp18r3 (1) rp18r2 (1) rp18r1 (1) rp18r0 (1) 0000 rpor10 06d4 ? ? ?rp21r4 (1) rp21r3 (1) rp21r2 (1) rp21r1 (1) rp21r0 (1) ? ? ?rp20r4 (1) rp20r3 (1) rp20r2 (1) rp20r1 (1) rp20r0 (1) 0000 rpor11 06d6 ? ? ?rp23r4 (1) rp23r3 (1) rp23r2 (1) rp23r1 (1) rp23r0 (1) ? ? ?rp22r4 (1) rp22r3 (1) rp22r2 (1) rp22r1 (1) rp22r0 (1) 0000 rpor12 06d8 ? ? ?rp25r4 (1) rp25r3 (1) rp25r2 (1) rp25r1 (1) rp25r0 (1) ? ? ?rp24r4 (1) rp24r3 (1) rp24r2 (1) rp24r1 (1) rp24r0 (1) 0000 legend: ? = unimplemented, read as ? 0 ? note 1: bits only available on the 44-pin devices; otherwise, they read as ? 0 ?.
pic24fj64ga004 family ds39881b-page 36 preliminary ? 2007 microchip technology inc. table 3-22: clock control register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rcon 0740 trapr iopuwr ? ? ? ? cm vregs extr swr swdten wdto sleep idle bor por (note 1) osccon 0742 ? cosc2 cosc1 cosc0 ? nosc2 nosc1 nosc0 clklock iolock lock ?cf ? soscen oswen (note 2) clkdiv 0744 roi doze2 doze1 doze0 dozen rcdiv2 rcdiv1 rcdiv0 ? ? ? ? ? ? ? ? 0100 osctun 0748 ? ? ? ? ? ? ? ? ? ? tun5 tun4 tun3 tun2 tun1 tun0 0000 legend: ? = unimplemented, read as ? 0 ? note 1: rcon register reset values dependent on type of reset. 2: osccon register reset values dependent on configuration fuses and by type of reset. table 3-23: nvm register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets nvmcon 0760 wr wren wrerr ? ? ? ? ? ?erase ? ? nvmop3 nvmop2 nvmop1 nvmop0 0000 (1) nvmkey 0766 ? ? ? ? ? ? ? ? nvmkey<7:0> 0000 legend: ? = unimplemented, read as ? 0 ? note 1: reset value shown is for por only. value on other reset states is dependent on the state of memory write or erase operations at the time of reset. table 3-24: pmd register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 b it 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pmd1 0770 t5md t4md t3md t2md t1md ? ? ? i2c1md u2md u1md spi2md spi1md ? ? adc1md 0000 pmd2 0772 ? ? ? ic5md ic4md ic3md ic2md ic1md ? ? ? oc5md oc4md oc3md oc2md oc1md 0000 pmd3 0774 ? ? ? ? ? cmpmd rtccmd pmpmd crcpmd ? ? ? ? ?i2c2md ? 0000 legend: ? = unimplemented, read as ? 0 ?
? 2007 microchip technology inc. preliminary ds39881b-page 37 pic24fj64ga004 family 3.2.5 software stack in addition to its use as a working register, the w15 reg- ister in pic24f devices is also used as a software stack pointer. the pointer always points to the first available free word and grows from lower to higher addresses. it pre-decrements for stack pops and post-increments for stack pushes, as shown in figure 3-4. note that for a pc push during any call instruction, the msb of the pc is zero-extended before the push, ensuring that the msb is always clear. the stack pointer limit value register (splim) associ- ated with the stack pointer sets an upper address boundary for the stack. splim is uninitialized at reset. as is the case for the stack pointer, splim<0> is forced to ? 0 ? because all stack operations must be word-aligned. whenever an ea is generated using w15 as a source or destination pointer, the resulting address is compared with the value in splim. if the contents of the stack pointer (w15) and the splim reg- ister are equal, and a push operation is performed, a stack error trap will not occur. the stack error trap will occur on a subsequent push operation. thus, for exam- ple, if it is desirable to cause a stack error trap when the stack grows beyond address 2000h in ram, initialize the splim with the value, 1ffeh. similarly, a stack pointer underflow (stack error) trap is generated when the stack pointer address is found to be less than 0800h. this prevents the stack from interfering with the special function register (sfr) space. a write to the splim register should not be immediately followed by an indirect read operation using w15. figure 3-4: call stack frame 3.3 interfacing program and data memory spaces the pic24f architecture uses a 24-bit wide program space and 16-bit wide data space. the architecture is also a modified harvard scheme, meaning that data can also be present in the program space. to use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. aside from normal execution, the pic24f architecture provides two methods by which program space can be accessed during operation: ? using table instructions to access individual bytes or words anywhere in the program space ? remapping a portion of the program space into the data space (program space visibility) table instructions allow an application to read or write to small areas of the program memory. this makes the method ideal for accessing data tables that need to be updated from time to time. it also allows access to all bytes of the program word. the remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look-ups from a large table of static data. it can only access the least significant word of the program word. 3.3.1 addressing program space since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. the solution depends on the interface method to be used. for table operations, the 8-bit table memory page address register (tblpag) is used to define a 32k word region within the program space. this is concatenated with a 16-bit ea to arrive at a full 24-bit program space address. in this format, the most significant bit of tblpag is used to determine if the operation occurs in the user memory (tblpag<7> = 0 ) or the configuration memory (tblpag<7> = 1 ). for remapping operations, the 8-bit program space visibility page address register (psvpag) is used to define a 16k word page in the program space. when the most significant bit of the ea is ? 1 ?, psvpag is con- catenated with the lower 15 bits of the ea to form a 23-bit program space address. unlike table operations, this limits remapping operations strictly to the user memory area. table 3-25 and figure 3-5 show how the program ea is created for table operations and remapping accesses from the data ea. here, p<23:0> refers to a program space word, whereas d<15:0> refers to a data space word. note: a pc push during exception processing will concatenate the srl register to the msb of the pc prior to the push. pc<15:0> 000000000 0 15 w15 (before call ) w15 (after call ) stack grows towards higher address 0000h pc<22:16> pop : [--w15] push : [w15++]
pic24fj64ga004 family ds39881b-page 38 preliminary ? 2007 microchip technology inc. table 3-25: program space address construction figure 3-5: data access from program space address generation access type access space program space address <23> <22:16> <15> <14:1> <0> instruction access (code execution) user 0 pc<22:1> 0 0xx xxxx xxxx xxxx xxxx xxx0 tblrd/tblwt (byte/word read/write) user tblpag<7:0> data ea<15:0> 0xxx xxxx xxxx xxxx xxxx xxxx configuration tblpag<7:0> data ea<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx program space visibility (block remap/read) user 0 psvpag<7:0> data ea<14:0> (1) 0 xxxx xxxx xxx xxxx xxxx xxxx note 1: data ea<15> is always ? 1 ? in this case, but is not used in calculating the program space address. bit 15 of the address is psvpag<0>. 0 program counter 23 bits 1 psvpag 8 bits ea 15 bits program counter (1) select tblpag 8 bits ea 16 bits byte select 0 0 1/0 user/configuration table operations (2) program space visibility (1) space select 24 bits 23 bits (remapping) 1/0 0 note 1: the lsb of program space addresses is always fixed as ? 0 ? in order to maintain word alignment of data in the program and data spaces. 2: table operations are not required to be word-aligned. table read operations are permitted in the configuration memory space.
? 2007 microchip technology inc. preliminary ds39881b-page 39 pic24fj64ga004 family 3.3.2 data access from program memory using table instructions the tblrdl and tblwtl instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. the tblrdh and tblwth instructions are the only method to read or write the upper 8 bits of a program space word as data. the pc is incremented by two for each successive 24-bit program word. this allows program memory addresses to directly map to data space addresses. program memory can thus be regarded as two 16-bit word-wide address spaces, residing side by side, each with the same address range. tblrdl and tblwtl access the space which contains the least significant data word, and tblrdh and tblwth access the space which contains the upper data byte. two table instructions are provided to move byte or word-sized (16-bit) data to and from program space. both function as either byte or word operations. 1. tblrdl (table read low): in word mode, it maps the lower word of the program space location (p<15:0>) to a data address (d<15:0>). in byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. the upper byte is selected when byte select is ? 1 ?; the lower byte is selected when it is ? 0 ?. 2. tblrdh (table read high): in word mode, it maps the entire upper word of a program address (p<23:16>) to a data address. note that d<15:8>, the ?phantom byte?, will always be ? 0 ?. in byte mode, it maps the upper or lower byte of the program word to d<7:0> of the data address, as above. note that the data will always be ? 0 ? when the upper ?phantom? byte is selected (byte select = 1 ). in a similar fashion, two table instructions, tblwth and tblwtl , are used to write individual bytes or words to a program space address. the details of their operation are explained in section 4.0 ?flash program memory? . for all table operations, the area of program memory space to be accessed is determined by the table memory page address register (tblpag). tblpag covers the entire program memory space of the device, including user and configuration spaces. when tblpag<7> = 0 , the table page is located in the user memory space. when tblpag<7> = 1 , the page is located in configuration space. figure 3-6: accessing program memory with table instructions note: only table read operations will execute in the configuration memory space, and only then, in implemented areas such as the device id. table write operations are not allowed. 0 8 16 23 00000000 00000000 00000000 00000000 ?phantom? byte tblrdh.b (wn<0> = 0 ) tblrdl.w tblrdl.b (wn<0> = 1 ) tblrdl.b (wn<0> = 0 ) 23 15 0 tblpag 02 000000h 800000h 020000h 030000h program space data ea<15:0> the address for the table operation is determined by the data ea within the page defined by the tblpag register. only read operations are shown; wr ite operations are also valid in the user memory area.
pic24fj64ga004 family ds39881b-page 40 preliminary ? 2007 microchip technology inc. 3.3.3 reading data from program memory using program space visibility the upper 32 kbytes of data space may optionally be mapped into any 16k word page of the program space. this provides transparent access of stored constant data from the data space without the need to use special instructions (i.e., tblrdl/h ). program space access through the data space occurs if the most significant bit of the data space ea is ? 1 ? and program space visibility is enabled by setting the psv bit in the cpu control register (corcon<2>). the location of the program memory space to be mapped into the data space is determined by the program space visibility page address register (psvpag). this 8-bit register defines any one of 256 possible pages of 16k words in program space. in effect, psvpag func- tions as the upper 8 bits of the program memory address, with the 15 bits of the ea functioning as the lower bits. note that by incrementing the pc by 2 for each program memory word, the lower 15 bits of data space addresses directly map to the lower 15 bits in the corresponding program space addresses. data reads to this area add an additional cycle to the instruction being executed, since two program memory fetches are required. although each data space address, 8000h and higher, maps directly into a corresponding program memory address (see figure 3-7), only the lower 16 bits of the 24-bit program word are used to contain the data. the upper 8 bits of any program space locations used as data should be programmed with ? 1111 1111 ? or ? 0000 0000 ? to force a nop . this prevents possible issues should the area of code ever be accidentally executed. for operations that use psv and are executed outside a repeat loop, the mov and mov.d instructions will require one instruction cycle in addition to the specified execution time. all other instructions will require two instruction cycles in addition to the specified execution time. for operations that use psv which are executed inside a repeat loop, there will be some instances that require two instruction cycles in addition to the specified execution time of the instruction: ? execution in the first iteration ? execution in the last iteration ? execution prior to exiting the loop due to an interrupt ? execution upon re-entering the loop after an interrupt is serviced any other iteration of the repeat loop will allow the instruction accessing data, using psv, to execute in a single cycle. figure 3-7: program space visibility operation note: psv access is temporarily disabled during table reads/writes. 23 15 0 psvpag data space program space 0000h 8000h ffffh 02 000000h 800000h 010000h 018000h when corcon<2> = 1 and ea<15> = 1 : psv area the data in the page designated by psvpag is mapped into the upper half of the data memory space.... data ea<14:0> ...while the lower 15 bits of the ea specify an exact address within the psv area. this corresponds exactly to the same lower 15 bits of the actual program space address.
? 2007 microchip technology inc. preliminary ds39881b-page 41 pic24fj64ga004 family 4.0 flash program memory the pic24fj64ga004 family of devices contains inter- nal flash program memory for storing and executing application code. the memory is readable, writable and erasable during normal operation over the entire v dd range. flash memory can be programmed in four ways: ? in-circuit serial programming (icsp) ? run-time self-programming (rtsp) ?jtag ? enhanced in-circuit serial programming (enhanced icsp) icsp allows a pic24fj64ga004 family device to be serially programmed while in the end application circuit. this is simply done with two lines for the programming clock and programming data (which are named pgcx and pgdx, respectively), and three other lines for power (v dd ), ground (v ss ) and master clear (mclr ). this allows customers to manufacture boards with unprogrammed devices and then program the micro- controller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. rtsp is accomplished using tblrd (table read) and tblwt (table write) instructions. with rtsp, the user may write program memory data in blocks of 64 instruc- tions (192 bytes) at a time, and erase program memory in blocks of 512 instructions (1536 bytes) at a time. 4.1 table instructions and flash programming regardless of the method used, all programming of flash memory is done with the table read and table write instructions. these allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. the 24-bit target address in the program memory is formed using the tblpag<7:0> bits and the effective address (ea) from a w register specified in the table instruction, as shown in figure 4-1. the tblrdl and the tblwtl instructions are used to read or write to bits<15:0> of program memory. tblrdl and tblwtl can access program memory in both word and byte modes. the tblrdh and tblwth instructions are used to read or write to bits<23:16> of program memory. tblrdh and tblwth can also access program memory in word or byte mode. figure 4-1: addressing for table registers note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the associated ?pic24f family reference manual? chapter. 0 program counter 24 bits program tblpag reg 8 bits working reg ea 16 bits using byte 24-bit ea 0 1/0 select table instruction counter using user/configuration space select
pic24fj64ga004 family ds39881b-page 42 preliminary ? 2007 microchip technology inc. 4.2 rtsp operation the pic24f flash program memory array is organized into rows of 64 instructions or 192 bytes. rtsp allows the user to erase blocks of eight rows (512 instructions) at a time and to program one row at a time. it is also possible to program single words. the 8-row erase blocks and single row write blocks are edge-aligned, from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively. when data is written to program memory using tblwt instructions, the data is not written directly to memory. instead, data written using table writes is stored in holding latches until the programming sequence is executed. any number of tblwt instructions can be executed and a write will be successfully performed. however, 64 tblwt instructions are required to write the full row of memory. to ensure that no data is corrupted during a write, any unused addresses should be programmed with ffffffh. this is because the holding latches reset to an unknown state, so if the addresses are left in the reset state, they may overwrite the locations on rows which were not rewritten. the basic sequence for rtsp programming is to set up a table pointer, then do a series of tblwt instructions to load the buffers. programming is performed by setting the control bits in the nvmcon register. data can be loaded in any order and the holding regis- ters can be written to multiple times before performing a write operation. subsequent writes, however, will wipe out any previous writes. all of the table write operations are single-word writes (2 instruction cycles), because only the buffers are writ- ten. a programming cycle is required for programming each row. 4.3 jtag operation the pic24f family supports jtag programming and boundary scan. boundary scan can improve the manu- facturing process by verifying pin-to-pcb connectivity. programming can be performed with industry standard jtag programmers supporting serial vector format (svf). 4.4 enhanced in-circuit serial programming enhanced in-circuit serial programming uses an on-board boot loader, known as the program executive, to manage the programming process. using an spi data frame format, the program executive can erase, program and verify program memory. for more information on enhanced icsp, see the device programming specification. 4.5 control registers there are two sfrs used to read and write the program flash memory: nvmcon and nvmkey. the nvmcon register (register 4-1) controls which blocks are to be erased, which memory type is to be programmed and when the programming cycle starts. nvmkey is a write-only register that is used for write protection. to start a pr ogramming or erase sequence, the user must consecutively write 55h and aah to the nvmkey register. refer to section 4.6 ?programming operations? for further details. 4.6 programming operations a complete programming sequence is necessary for programming or erasing the internal flash in rtsp mode. during a programming or erase operation, the processor stalls (waits) until the operation is finished. setting the wr bit (nvmcon<15>) starts the opera- tion and the wr bit is automatically cleared when the operation is finished. configuration word values are stored in the last two locations of program memory. performing a page erase operation on the last page of program memory clears these values and enables code protection. as a result, avoid performing page erase operations on the last page of program memory. note: writing to a page multiple times without erasing it is not recommended.
? 2007 microchip technology inc. preliminary ds39881b-page 43 pic24fj64ga004 family register 4-1: nvmcon: flash memory control register r/so-0 (1) r/w -0 (1) r/w -0 (1) u-0 u-0 u-0 u-0 u-0 wr wren wrerr ? ? ? ? ? bit 15 bit 8 u-0 r/w -0 (1) u-0 u-0 r/w -0 (1) r/w -0 (1) r/w -0 (1) r/w -0 (1) ? erase ? ?nvmop3 (2) nvmop2 (2) nvmop1 (2) nvmop0 (2) bit 7 bit 0 legend: so = set-only bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 wr: write control bit (1) 1 = initiates a flash memory program or erase operation. the operation is self-timed and the bit is cleared by hardware once operation is complete. 0 = program or erase operation is complete and inactive bit 14 wren: write enable bit (1) 1 = enable flash program/erase operations 0 = inhibit flash program/erase operations bit 13 wrerr: write sequence error flag bit (1) 1 = an improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the wr bit) 0 = the program or erase operation completed normally bit 12-7 unimplemented: read as ? 0 ? bit 6 erase: erase/program enable bit (1) 1 = perform the erase operation specified by nvmop3:nvmop0 on the next wr command 0 = perform the program operation specified by nvmop3:nvmop0 on the next wr command bit 5-4 unimplemented: read as ? 0 ? bit 3-0 nvmop3:nvmop0: nvm operation select bits (1,2) 1111 = memory bulk erase operation (erase = 1 ) or no operation (erase = 0 ) (3) 0011 = memory word program operation (erase = 0 ) or no operation (erase = 1 ) 0010 = memory page erase operation (erase = 1 ) or no operation (erase = 0 ) 0001 = memory row program operation (erase = 0 ) or no operation (erase = 1 ) note 1: these bits can only be reset on por. 2: all other combinations of nvmop3:nvmop0 are unimplemented. 3: available in icsp? mode only. refer to device programming specification.
pic24fj64ga004 family ds39881b-page 44 preliminary ? 2007 microchip technology inc. 4.6.1 programming algorithm for flash program memory the user can program one row of program flash memory at a time. to do this, it is necessary to erase the 8-row erase block containing the desired row. the general process is: 1. read eight rows of program memory (512 instructions) and store in data ram. 2. update the program data in ram with the desired new data. 3. erase the block (see example 4-1): a) set the nvmop bits (nvmcon<3:0>) to ? 0010 ? to configure for block erase. set the erase (nvmcon<6>) and wren (nvmcon<14>) bits. b) write the starting address of the block to be erased into the tblpag and w registers. c) write 55h to nvmkey. d) write aah to nvmkey. e) set the wr bit (nvmcon<15>). the erase cycle begins and the cpu stalls for the dura- tion of the erase cycle. when the erase is done, the wr bit is cleared automatically. 4. write the first 64 instructions from data ram into the program memory buffers (see example 4-1). 5. write the program block to flash memory: a) set the nvmop bits to ? 0001 ? to configure for row programming. clear the erase bit and set the wren bit. b) write 55h to nvmkey. c) write aah to nvmkey. d) set the wr bit. the programming cycle begins and the cpu stalls for the duration of the write cycle. when the write to flash memory is done, the wr bit is cleared automatically. 6. repeat steps 4 and 5, using the next available 64 instructions from the block in data ram by incrementing the value in tblpag, until all 512 instructions are written back to flash memory. for protection against accidental operations, the write initiate sequence for nvmkey must be used to allow any erase or program operation to proceed. after the programming command has been executed, the user must wait for the programming time until programming is complete. the two instructions following the start of the programming sequence should be nop s, as shown in example 4-3. example 4-1: erasing a program memory block ; set up nvmcon for block erase operation mov #0x4042, w0 ; mov w0, nvmcon ; initialize nvmcon ; init pointer to row to be erased mov #tblpage(prog_addr), w0 ; mov w0, tblpag ; initialize pm page boundary sfr mov #tbloffset(prog_addr), w0 ; initialize in-page ea[15:0] pointer tblwtl w0, [w0] ; set base address of erase block disi #5 ; block all interrupts with priority <7 ; for next 5 instructions mov #0x55, w0 mov w0, nvmkey ; write the 55 key mov #0xaa, w1 ; mov w1, nvmkey ; write the aa key bset nvmcon, #wr ; start the erase sequence nop ; insert two nops after the erase nop ; command is asserted
? 2007 microchip technology inc. preliminary ds39881b-page 45 pic24fj64ga004 family example 4-2: loading the write buffers example 4-3: initiating a programming sequence ; set up nvmcon for row programming operations mov #0x4001, w0 ; mov w0, nvmcon ; initialize nvmcon ; set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled mov #0x0000, w0 ; mov w0, tblpag ; initialize pm page boundary sfr mov #0x6000, w0 ; an example program memory address ; perform the tblwt instructions to write the latches ; 0th_program_word mov #low_word_0, w2 ; mov #high_byte_0, w3 ; tblwtl w2, [w0] ; write pm low word into program latch tblwth w3, [w0++] ; write pm high byte into program latch ; 1st_program_word mov #low_word_1, w2 ; mov #high_byte_1, w3 ; tblwtl w2, [w0] ; write pm low word into program latch tblwth w3, [w0++] ; write pm high byte into program latch ; 2nd_program_word mov #low_word_2, w2 ; mov #high_byte_2, w3 ; tblwtl w2, [w0] ; write pm low word into program latch tblwth w3, [w0++] ; write pm high byte into program latch ? ? ? ; 63rd_program_word mov #low_word_31, w2 ; mov #high_byte_31, w3 ; tblwtl w2, [w0] ; write pm low word into program latch tblwth w3, [w0] ; write pm high byte into program latch disi #5 ; block all interrupts with priority <7 ; for next 5 instructions mov #0x55, w0 mov w0, nvmkey ; write the 55 key mov #0xaa, w1 ; mov w1, nvmkey ; write the aa key bset nvmcon, #wr ; start the erase sequence btsc nvmcon, #15 ; and wait for it to be bra $-2 ; completed
pic24fj64ga004 family ds39881b-page 46 preliminary ? 2007 microchip technology inc. 4.6.2 programming a single word of flash program memory if a flash location has been erased, it can be pro- grammed using table write instructions to write an instruction word (24-bit) into the write latch. the tblpag register is loaded with the 8 most significant bytes of the flash address. the tblwtl and tblwth instructions write the desired data into the write latches and specify the lower 16 bits of the program memory address to write to. to configure the nvmcon register for a word write, set the nvmop bits (nvmcon<3:0>) to ? 0011 ?. the write is performed by executing the unlock sequence and setting the wr bit (see example 4-4). example 4-4: programming a single word of flash program memory ; setup a pointer to data program memory mov #tblpage(prog_addr), w0 ; mov w0, tblpag ;initialize pm page boundary sfr mov #tbloffset(prog_addr), w0 ;initialize a register with program memory address mov #low_word_n, w2 ; mov #high_byte_n, w3 ; tblwtl w2, [w0] ; write pm low word into program latch tblwth w3, [w0++] ; write pm high byte into program latch ; setup nvmcon for programming one word to data program memory mov #0x4003, w0 ; mov w0, nvmcon ; set nvmop bits to 0011 disi #5 ; disable interrupts while the key sequence is written mov #0x55, w0 ; write the key sequence mov w0, nvmkey mov #0xaa, w0 mov w0, nvmkey bset nvmcon, #wr ; start the write cycle
? 2007 microchip technology inc. preliminary ds39881b-page 47 pic24fj64ga004 family 5.0 resets the reset module combines all reset sources and controls the device master reset signal, sysrst . the following is a list of device reset sources: ? por: power-on reset ?mclr : pin reset ?swr: reset instruction ? wdt: watchdog timer reset ? bor: brown-out reset ? trapr: trap conflict reset ? iopuwr: illegal opcode reset ? uwr: uninitialized w register reset a simplified block diagram of the reset module is shown in figure 5-1. any active source of reset will make the sysrst signal active. many registers associated with the cpu and peripherals are forced to a known reset state. most registers are unaffected by a reset; their status is unknown on por and unchanged by all other resets. all types of device reset will set a corresponding status bit in the rcon register to indicate the type of reset (see register 5-1). a power-on reset will clear all bits except for the bor and por bits (rcon<1:0>) which are set. the user may set or clear any bit at any time during code execution. the rcon bits only serve as status bits. setting a particular reset status bit in software will not cause a device reset to occur. the rcon register also has other bits associated with the watchdog timer and device power-saving states. the function of these bits is discussed in other sections of this manual. figure 5-1: reset system block diagram note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the associated ?pic24f family reference manual? chapter. note: refer to the specific peripheral or cpu section of this manual for register reset states. note: the status bits in the rcon register should be cleared after they are read so that the next rcon register value after a device reset will be meaningful. mclr v dd v dd rise detect por sleep or idle brown-out reset enable voltage regulator reset instruction wdt module glitch filter bor trap conflict illegal opcode uninitialized w register sysrst
pic24fj64ga004 family ds39881b-page 48 preliminary ? 2007 microchip technology inc. register 5-1: rcon: reset control register (1) r/w -0 r/w -0 u-0 u-0 u-0 u-0 r/w -0 r/w -0 trapr iopuwr ? ? ? ?cmvregs bit 15 bit 8 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -1 r/w -1 extr swr swdten (2) wdto sleep idle bor por bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 trapr: trap reset flag bit 1 = a trap conflict reset has occurred 0 = a trap conflict reset has not occurred bit 14 iopuwr: illegal opcode or uninitialized w access reset flag bit 1 = an illegal opcode detection, an illegal address mode or uninitialized w register used as an address pointer caused a reset 0 = an illegal opcode or uninitialized w reset has not occurred bit 13-10 unimplemented: read as ? 0 ? bit 9 cm: configuration word mismatch reset flag bit 1 = a configuration word mismatch reset has occurred 0 = a configuration word mismatch reset has not occurred bit 8 vregs: voltage regulator standby enable bit 1 = regulator remains active during sleep 0 = regulator goes to standby during sleep bit 7 extr: external reset (mclr ) pin bit 1 = a master clear (pin) reset has occurred 0 = a master clear (pin) reset has not occurred bit 6 swr: software reset (instruction) flag bit 1 = a reset instruction has been executed 0 = a reset instruction has not been executed bit 5 swdten: software enable/disable of wdt bit (2) 1 = wdt is enabled 0 = wdt is disabled bit 4 wdto: watchdog timer time-out flag bit 1 = wdt time-out has occurred 0 = wdt time-out has not occurred bit 3 sleep: wake from sleep flag bit 1 = device has been in sleep mode 0 = device has not been in sleep mode bit 2 idle: wake-up from idle flag bit 1 = device has been in idle mode 0 = device has not been in idle mode bit 1 bor: brown-out reset flag bit 1 = a brown-out reset has occurred. note that bor is also set after a power-on reset. 0 = a brown-out reset has not occurred bit 0 por: power-on reset flag bit 1 = a power-up reset has occurred 0 = a power-up reset has not occurred note 1: all of the reset status bits may be set or cleared in software. setting one of these bits in software does not cause a device reset. 2: if the fwdten configuration bit is ? 1 ? (unprogrammed), the wdt is always enabled, regardless of the swdten bit setting.
? 2007 microchip technology inc. preliminary ds39881b-page 49 pic24fj64ga004 family table 5-1: reset flag bit operation 5.1 clock source selection at reset if clock switching is enabled, the system clock source at device reset is chosen as shown in table 5-2. if clock switching is disabled, the system clock source is always selected according to the oscillator configuration bits. refer to section 7.0 ?oscillator configuration? for further details. table 5-2: oscillator selection vs. type of reset (clock switching enabled) 5.2 device reset times the reset times for various types of device reset are summarized in table 5-3. note that the system reset signal, sysrst , is released after the por and pwrt delay times expire. the time that the device actually begins to execute code will also depend on the system oscillator delays, which include the oscillator start-up timer (ost) and the pll lock time. the ost and pll lock times occur in parallel with the applicable sysrst delay times. the fscm delay determines the time at which the fscm begins to monitor the system clock source after the sysrst signal is released. flag bit setting event clearing event trapr (rcon<15>) trap conflict event por iopuwr (rcon<14>) illegal opcode or uninitialized w register access por extr (rcon<7>) mclr reset por swr (rcon<6>) reset instruction por wdto (rcon<4>) wdt time-out pwrsav instruction, por sleep (rcon<3>) pwrsav #sleep instruction por idle (rcon<2>) pwrsav #idle instruction por bor (rcon<1>) por, bor ? por (rcon<0>) por ? note: all reset flag bits may be set or cleared by the user software. reset type clock source determinant por oscillator configuration bits (cw2<10:8>) bor mclr cosc control bits (osccon<14:12>) wdto swr
pic24fj64ga004 family ds39881b-page 50 preliminary ? 2007 microchip technology inc. table 5-3: reset delay times for various device resets reset type clock source sysrst delay system clock delay fscm delay notes por ec, frc, frcdiv, lprc t por + t startup + t rst ?? 1, 2, 3 ecpll, frcpll t por + t startup + t rst t lock t fscm 1, 2, 3, 5, 6 xt, hs, sosc t por + t startup + t rst t ost t fscm 1, 2, 3, 4, 6 xtpll, hspll t por + t startup + t rst t ost + t lock t fscm 1, 2, 3, 4, 5, 6 bor ec, frc, frcdiv, lprc t startup + t rst ?? 2, 3 ecpll, frcpll t startup + t rst t lock t fscm 2, 3, 5, 6 xt, hs, sosc t startup + t rst t ost t fscm 2, 3, 4, 6 xtpll, hspll t startup + t rst t ost + t lock t fscm 2, 3, 4, 5, 6 mclr any clock t rst ?? 3 wdt any clock t rst ?? 3 software any clock t rst ?? 3 illegal opcode any clock t rst ?? 3 uninitialized w any clock t rst ?? 3 trap conflict any clock t rst ?? 3 note 1: t por = power-on reset delay (10 s nominal). 2: t startup = t vreg (10 s nominal) if on-chip regulator is enabled or t pwrt (64 ms nominal) if on-chip regulator is disabled. 3: t rst = internal state reset time (20 s nominal). 4: t ost = oscillator start-up timer. a 10-bit counter counts 1024 oscillator periods before releasing the oscillator clock to the system. 5: t lock = pll lock time (20 s nominal). 6: t fscm = fail-safe clock monitor delay (100 s nominal).
? 2007 microchip technology inc. preliminary ds39881b-page 51 pic24fj64ga004 family 5.2.1 por and long oscillator start-up times the oscillator start-up circuitry and its associated delay timers are not linked to the device reset delays that occur at power-up. some crystal circuits (especially low-frequency crystals) will have a relatively long start-up time. therefore, one or more of the following conditions is possible after sysrst is released: ? the oscillator circuit has not begun to oscillate. ? the oscillator start-up timer has not expired (if a crystal oscillator is used). ? the pll has not achieved a lock (if pll is used). the device will not begin to execute code until a valid clock source has been released to the system. there- fore, the oscillator and pll start-up delays must be considered when the reset delay time must be known. 5.2.2 fail-safe clock monitor (fscm) and device resets if the fscm is enabled, it will begin to monitor the system clock source when sysrst is released. if a valid clock source is not available at this time, the device will automatically switch to the frc oscillator and the user can switch to the desired crystal oscillator in the trap service routine. 5.2.2.1 fscm delay for crystal and pll clock sources when the system clock source is provided by a crystal oscillator and/or the pll, a small delay, t fscm , will automatically be inserted after the por and pwrt delay times. the fscm will not begin to monitor the system clock source until this delay expires. the fscm delay time is nominally 100 s and provides additional time for the oscillator and/or pll to stabilize. in most cases, the fscm delay will prevent an oscillator failure trap at a device reset when the pwrt is disabled. 5.3 special function register reset states most of the special function registers (sfrs) associ- ated with the pic24f cpu and peripherals are reset to a particular value at a device reset. the sfrs are grouped by their peripheral or cpu function and their reset values are specified in each section of this manual. the reset value for each sfr does not depend on the type of reset, with the exception of four registers. the reset value for the reset control register, rcon, will depend on the type of device reset. the reset value for the oscillator control register, osccon, will depend on the type of reset and the programmed values of the fnosc bits in the cw2 register (see table 5-2). the rcfgcal and nvmcon registers are only affected by a por.
pic24fj64ga004 family ds39881b-page 52 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds39881b-page 53 pic24fj64ga004 family 6.0 interrupt controller the pic24f interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the pic24f cpu. it has the following features: ? up to 8 processor exceptions and software traps ? 7 user-selectable priority levels ? interrupt vector table (ivt) with up to 118 vectors ? a unique vector for each interrupt or exception source ? fixed priority within a specified user priority level ? alternate interrupt vector table (aivt) for debug support ? fixed interrupt entry and return latencies 6.1 interrupt vector table the interrupt vector table (ivt) is shown in figure 6-1. the ivt resides in program memory, starting at location 000004h. the ivt contains 126 vectors, consisting of 8 non-maskable trap vectors, plus up to 118 sources of interrupt. in general, each interrupt source has its own vector. each interrupt vector contains a 24-bit wide address. the value programmed into each interrupt vector location is the starting address of the associated interrupt service routine (isr). interrupt vectors are prioritized in terms of their natural priority; this is linked to their position in the vector table. all other things being equal, lower addresses have a higher natural priority. for example, the interrupt asso- ciated with vector 0 will take priority over interrupts at any other vector address. pic24fj64ga004 family devices implement non-maskable traps and unique interrupts. these are summarized in table 6-1 and table 6-2. 6.1.1 alternate interrupt vector ta b l e the alternate interrupt vector table (aivt) is located after the ivt, as shown in figure 6-1. access to the aivt is provided by the altivt control bit (intcon2<15>). if the altivt bit is set, all interrupt and exception processes will use the alternate vectors instead of the default vectors. the alternate vectors are organized in the same manner as the default vectors. the aivt supports emulation and debugging efforts by providing a means to switch between an application and a support environment without requiring the inter- rupt vectors to be reprogrammed. this feature also enables switching between applications for evaluation of different software algorithms at run time. if the aivt is not needed, the aivt should be programmed with the same addresses used in the ivt. 6.2 reset sequence a device reset is not a true exception because the interrupt controller is not involved in the reset process. the pic24f devices clear their registers in response to a reset which forces the pc to zero. the micro- controller then begins program execution at location 000000h. the user programs a goto instruction at the reset address, which redirects program execution to the appropriate start-up routine. note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the associated ?pic24f family reference manual? chapter. note: any unimplemented or unused vector locations in the ivt and aivt should be programmed with the address of a default interrupt handler routine that contains a reset instruction.
pic24fj64ga004 family ds39881b-page 54 preliminary ? 2007 microchip technology inc. figure 6-1: pic24f interrupt vector table table 6-1: trap vector details vector number ivt address aivt address trap source 0 000004h 000104h reserved 1 000006h 000106h oscillator failure 2 000008h 000108h address error 3 00000ah 00010ah stack error 4 00000ch 00010ch math error 5 00000eh 00010eh reserved 6 000010h 000110h reserved 7 000012h 0001172h reserved reset ? goto instruction 000000h reset ? goto address 000002h reserved 000004h oscillator fail trap vector address error trap vector stack error trap vector math error trap vector reserved reserved reserved interrupt vector 0 000014h interrupt vector 1 ? ? ? interrupt vector 52 00007ch interrupt vector 53 00007eh interrupt vector 54 000080h ? ? ? interrupt vector 116 0000fch interrupt vector 117 0000feh reserved 000100h reserved 000102h reserved oscillator fail trap vector address error trap vector stack error trap vector math error trap vector reserved reserved reserved interrupt vector 0 000114h interrupt vector 1 ? ? ? interrupt vector 52 00017ch interrupt vector 53 00017eh interrupt vector 54 000180h ? ? ? interrupt vector 116 interrupt vector 117 0001feh start of code 000200h decreasing natural order priority interrupt vector table (ivt) (1) alternate interrupt vector table (aivt) (1) note 1: see table 6-2 for the interrupt vector list.
? 2007 microchip technology inc. preliminary ds39881b-page 55 pic24fj64ga004 family table 6-2: implemented interrupt vectors interrupt source vector number ivt address aivt address interrupt bit locations flag enable priority adc1 conversion done 13 00002eh 00012eh ifs0<13> iec0<13> ipc3<6:4> comparator event 18 000038h 000138h ifs1<2> iec1<2> ipc4<10:8> crc generator 67 00009ah 00019ah ifs4<3> iec4<3> ipc16<14:12> external interrupt 0 0 000014h 000114h ifs0<0> iec0<0> ipc0<2:0> external interrupt 1 20 00003ch 00013ch ifs1<4> iec1<4> ipc5<2:0> external interrupt 2 29 00004eh 00014eh ifs1<13> iec1<13> ipc7<6:4> i2c1 master event 17 000036h 000136h ifs1<1> iec1<1> ipc4<6:4> i2c1 slave event 16 000034h 000034h ifs1<0> iec1<0> ipc4<2:0> i2c2 master event 50 000078h 000178h ifs3<2> iec3<2> ipc12<10:8> i2c2 slave event 49 000076h 000176h ifs3<1> iec3<1> ipc12<6:4> input capture 1 1 000016h 000116h ifs0<1> iec0<1> ipc0<6:4> input capture 2 5 00001eh 00011eh ifs0<5> iec0<5> ipc1<6:4> input capture 3 37 00005eh 00015eh ifs2<5> iec2<5> ipc9<6:4> input capture 4 38 000060h 000160h ifs2<6> iec2<6> ipc9<10:8> input capture 5 39 000062h 000162h ifs2<7> iec2<7> ipc9<14:12> input change notification 19 00003ah 00013ah ifs1<3> iec1<3> ipc4<14:12> output compare 1 2 000018h 000118h ifs0<2> iec0<2> ipc0<10:8> output compare 2 6 000020h 000120h ifs0<6> iec0<6> ipc1<10:8> output compare 3 25 000046h 000146h ifs1<9> iec1<9> ipc6<6:4> output compare 4 26 000048h 000148h ifs1<10> iec1<10> ipc6<10:8> output compare 5 41 000066h 000166h ifs2<9> iec2<9> ipc10<6:4> parallel master port 45 00006eh 00016eh ifs2<13> iec2<13> ipc11<6:4> real-time clock/calendar 62 000090h 000190h ifs3<14> iec3<13> ipc15<10:8> spi1 error 9 000026h 000126h ifs0<9> iec0<9> ipc2<6:4> spi1 event 10 000028h 000128h ifs0<10> iec0<10> ipc2<10:8> spi2 error 32 000054h 000154h ifs2<0> iec0<0> ipc8<2:0> spi2 event 33 000056h 000156h ifs2<1> iec2<1> ipc8<6:4> timer1 3 00001ah 00011ah ifs0<3> iec0<3> ipc0<14:12> timer2 7 000022h 000122h ifs0<7> iec0<7> ipc1<14:12> timer3 8 000024h 000124h ifs0<8> iec0<8> ipc2<2:0> timer4 27 00004ah 00014ah ifs1<11> iec1<11> ipc6<14:12> timer5 28 00004ch 00014ch ifs1<12> iec1<12> ipc7<2:0> uart1 error 65 000096h 000196h ifs4<1> iec4<1> ipc16<6:4> uart1 receiver 11 00002ah 00012ah ifs0<11> iec0<11> ipc2<14:12> uart1 transmitter 12 00002ch 00012ch ifs0<12> iec0<12> ipc3<2:0> uart2 error 66 000098h 000198h ifs4<2> iec4<2> ipc16<10:8> uart2 receiver 30 000050h 000150h ifs1<14> iec1<14> ipc7<10:8> uart2 transmitter 31 000052h 000152h ifs1<15> iec1<15> ipc7<14:12> lvd low-voltage detect 72 0000a4h 000124h ifs4<8> iec4<8> ipc17<2:0>
pic24fj64ga004 family ds39881b-page 56 preliminary ? 2007 microchip technology inc. 6.3 interrupt control and status registers the pic24fj64ga004 family of devices implement a total of 28 registers for the interrupt controller: ? intcon1 ? intcon2 ? ifs0 through ifs4 ? iec0 through iec4 ? ipc0 through ipc12, ipc15, ipc16 and ipc18 global interrupt control functions are controlled from intcon1 and intcon2. intcon1 contains the inter- rupt nesting disable (nstdis) bit, as well as the control and status flags for the processor trap sources. the intcon2 register controls the external interrupt request signal behavior and the use of the alternate interrupt vector table. the ifsx registers maintain all of the interrupt request flags. each source of interrupt has a status bit which is set by the respective peripherals, or external signal, and is cleared via software. the iecx registers maintain all of the interrupt enable bits. these control bits are used to individually enable interrupts from the peripherals or external signals. the ipcx registers are used to set the interrupt priority level for each source of interrupt. each user interrupt source can be assigned to one of eight priority levels. the interrupt sources are assigned to the ifsx, iecx and ipcx registers in the same sequence that they are listed in table 6-2. for example, the int0 (external interrupt 0) is shown as having a vector number and a natural order priority of 0. thus, the int0if status bit is found in ifs0<0>, the int0ie enable bit in iec0<0> and the int0ip<2:0> priority bits in the first position of ipc0 (ipc0<2:0>). although they are not specifically part of the interrupt control hardware, two of the cpu control registers con- tain bits that control interrupt functionality. the alu status register (sr) contains the ipl2:ipl0 bits (sr<7:5>). these indicate the current cpu interrupt priority level. the user may change the current cpu priority level by writing to the ipl bits. the corcon register contains the ipl3 bit, which together with ipl2:ipl0, also indicates the current cpu priority level. ipl3 is a read-only bit so that trap events cannot be masked by the user software. all interrupt registers are described in register 6-1 through register 6-29, in the following pages.
? 2007 microchip technology inc. preliminary ds39881b-page 57 pic24fj64ga004 family register 6-1: sr: alu status register (in cpu) u-0 u-0 u-0 u-0 u-0 u-0 u-0 r-0 ? ? ? ? ? ? ?dc (1) bit 15 bit 8 r/w -0 r/w -0 r/w -0 r-0 r/w -0 r/w -0 r/w -0 r/w -0 ipl2 (2,3) ipl1 (2,3) ipl0 (2,3) ra (1) n (1) ov (1) z (1) c (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-5 ipl2:ipl0: cpu interrupt priority level status bits (2,3) 111 = cpu interrupt priority level is 7 (15). user interrupts disabled. 110 = cpu interrupt priority level is 6 (14) 101 = cpu interrupt priority level is 5 (13) 100 = cpu interrupt priority level is 4 (12) 011 = cpu interrupt priority level is 3 (11) 010 = cpu interrupt priority level is 2 (10) 001 = cpu interrupt priority level is 1 (9) 000 = cpu interrupt priority level is 0 (8) note 1: see register 2-1 for the description of the remaining bit (s) that are not dedicated to interrupt control functions. 2: the ipl bits are concatenated with the ipl3 bit (corcon<3>) to form the cpu interrupt priority level. the value in parentheses indicates the interrupt priority level if ipl3 = 1 . 3: the ipl status bits are read-only when nstdis (intcon1<15>) = 1 . register 6-2: corcon: cpu control register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 r/c-0 r/w -0 u-0 u-0 ? ? ? ?ipl3 (2) psv (1) ? ? bit 7 bit 0 legend: c = clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 8 ipl3: cpu interrupt priority level status bit (2) 1 = cpu interrupt priority level is greater than 7 0 = cpu interrupt priority level is 7 or less note 1: see register 2-2 for the description of remaining bit (s) that are not dedicated to interrupt control functions. 2: the ipl3 bit is concatenated with the ipl2:ipl0 bits (sr<7:5>) to form the cpu interrupt priority level.
pic24fj64ga004 family ds39881b-page 58 preliminary ? 2007 microchip technology inc. register 6-3: intcon1: interrupt control register 1 r/w -0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 nstdis ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 u-0 ? ? ? matherr addrerr stkerr oscfail ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 nstdis: interrupt nesting disable bit 1 = interrupt nesting is disabled 0 = interrupt nesting is enabled bit 14-5 unimplemented: read as ? 0 ? bit 4 matherr: arithmetic error trap status bit 1 = overflow trap has occurred 0 = overflow trap has not occurred bit 3 addrerr: address error trap status bit 1 = address error trap has occurred 0 = address error trap has not occurred bit 2 stkerr: stack error trap status bit 1 = stack error trap has occurred 0 = stack error trap has not occurred bit 1 oscfail: oscillator failure trap status bit 1 = oscillator failure trap has occurred 0 = oscillator failure trap has not occurred bit 0 unimplemented: read as ? 0 ?
? 2007 microchip technology inc. preliminary ds39881b-page 59 pic24fj64ga004 family register 6-4: intcon2: interrupt control register 2 r/w -0 r-0 u-0 u-0 u-0 u-0 u-0 u-0 altivt disi ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 ? ? ? ? ? int2ep int1ep int0ep bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 altivt: enable alternate interrupt vector table bit 1 = use alternate interrupt vector table 0 = use standard (default) vector table bit 14 disi: disi instruction status bit 1 = disi instruction is active 0 = disi instruction is not active bit 13-3 unimplemented: read as ? 0 ? bit 2 int2ep: external interrupt 2 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge bit 1 int1ep: external interrupt 1 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge bit 0 int0ep: external interrupt 0 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge
pic24fj64ga004 family ds39881b-page 60 preliminary ? 2007 microchip technology inc. register 6-5: ifs0: interrupt flag status register 0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ad1if u1txif u1rxif spi1if spf1if t3if bit 15 bit 8 r/w -0 r/w -0 r/w -0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 t2if oc2if ic2if ? t1if oc1if ic1if int0if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 ad1if: a/d conversion complete interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 12 u1txif: uart1 transmitter interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 11 u1rxif: uart1 receiver interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 10 spi1if: spi1 event interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 9 spf1if: spi1 fault interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 8 t3if: timer3 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 7 t2if: timer2 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 6 oc2if: output compare channel 2 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 5 ic2if: input capture channel 2 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 4 unimplemented: read as ? 0 ? bit 3 t1if: timer1 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 2 oc1if: output compare channel 1 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 1 ic1if: input capture channel 1 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 int0if: external interrupt 0 flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred
? 2007 microchip technology inc. preliminary ds39881b-page 61 pic24fj64ga004 family register 6-6: ifs1: interrupt flag status register 1 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 u-0 u2txif u2rxif int2if t5if t4if oc4if oc3if ? bit 15 bit 8 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ? int1if cnif cmif mi2c1if si2c1if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 u2txif: uart2 transmitter interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 14 u2rxif: uart2 receiver interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 13 int2if: external interrupt 2 flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 12 t5if: timer5 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 11 t4if: timer4 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 10 oc4if: output compare channel 4 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 9 oc3if: output compare channel 3 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 8-5 unimplemented: read as ? 0 ? bit 4 int1if: external interrupt 1 flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 3 cnif: input change notification interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 2 cmif: comparator interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 1 mi2c1if: master i2c1 event interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 si2c1if: slave i2c1 event interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred
pic24fj64ga004 family ds39881b-page 62 preliminary ? 2007 microchip technology inc. register 6-7: ifs2: interrupt flag status register 2 u-0 u-0 r/w -0 u-0 u-0 u-0 r/w -0 u-0 ? ?pmpif ? ? ?oc5if ? bit 15 bit 8 r/w -0 r/w -0 r/w -0 u-0 u-0 u-0 r/w -0 r/w -0 ic5if ic4if ic3if ? ? ? spi2if spf2if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 pmpif: parallel master port interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 12-10 unimplemented: read as ? 0 ? bit 9 oc5if: output compare channel 5 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 8 unimplemented: read as ? 0 ? bit 7 ic5if: input capture channel 5 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 6 ic4if: input capture channel 4 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 5 ic3if: input capture channel 3 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 4-2 unimplemented: read as ? 0 ? bit 1 spi2if: spi2 event interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 spi2if: spi2 fault interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred
? 2007 microchip technology inc. preliminary ds39881b-page 63 pic24fj64ga004 family register 6-8: ifs3: interrupt flag status register 3 u-0 r/w -0 u-0 u-0 u-0 u-0 u-0 u-0 ?rtcif ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w -0 r/w -0 u-0 ? ? ? ? ? mi2c2if si2c2if ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14 rtcif: real-time clock/calendar interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 13-3 unimplemented: read as ? 0 ? bit 2 mi2c2if: master i2c2 event interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 1 si2c2if: slave i2c2 event interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 unimplemented: read as ? 0 ?
pic24fj64ga004 family ds39881b-page 64 preliminary ? 2007 microchip technology inc. register 6-9: ifs4: interrupt flag status register 4 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w -0 ? ? ? ? ? ? ?lvdif bit 15 bit 8 u-0 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 u-0 ? ? ? ? crcif u2erif u1erif ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-9 unimplemented: read as ? 0 ? bit 8 lvdif: low-voltage detect interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 7-4 unimplemented: read as ? 0 ? bit 3 crcif: crc generator interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 2 u2erif: uart2 error interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 1 u1erif: uart1 error interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 unimplemented: read as ? 0 ?
? 2007 microchip technology inc. preliminary ds39881b-page 65 pic24fj64ga004 family register 6-10: iec0: interrupt enable control register 0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ad1ie u1txie u1rxie spi1ie spf1ie t3ie bit 15 bit 8 r/w -0 r/w -0 r/w -0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 t2ie oc2ie ic2ie ? t1ie oc1ie ic1ie int0ie (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 ad1ie: a/d conversion complete interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 12 u1txie: uart1 transmitter interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 11 u1rxie: uart1 receiver interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 10 spi1ie: spi1 transfer complete interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 9 spf1ie: spi1 fault interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 8 t3ie: timer3 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 7 t2ie: timer2 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 6 oc2ie: output compare channel 2 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 5 ic2ie: input capture channel 2 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 4 unimplemented: read as ? 0 ? bit 3 t1ie: timer1 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 2 oc1ie: output compare channel 1 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 1 ic1ie: input capture channel 1 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 0 int0ie: external interrupt 0 enable bit (1) 1 = interrupt request enabled 0 = interrupt request not enabled note 1: if intxie = 1 , this external interrupt input must be configured to an available rpx pin. see section 9.4 ?peripheral pin select? for more information.
pic24fj64ga004 family ds39881b-page 66 preliminary ? 2007 microchip technology inc. register 6-11: iec1: interrupt enable control register 1 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 u-0 u2txie u2rxie int2ie (1) t5ie t4ie oc4ie oc3ie ? bit 15 bit 8 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ?int1ie (1) cnie cmie mi2c1ie si2c1ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 u2txie: uart2 transmitter interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 14 u2rxie: uart2 receiver interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 13 int2ie: external interrupt 2 enable bit (1) 1 = interrupt request enabled 0 = interrupt request not enabled bit 12 t5ie: timer5 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 11 t4ie: timer4 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 10 oc4ie: output compare channel 4 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 9 oc3ie: output compare channel 3 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 8-5 unimplemented: read as ? 0 ? bit 4 int1ie: external interrupt 1 enable bit (1) 1 = interrupt request enabled 0 = interrupt request not enabled bit 3 cnie: input change notification interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 2 cmie: comparator interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 1 mi2c1ie: master i2c1 event interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 0 si2c1ie: slave i2c1 event interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled note 1: if intxie = 1 , this external interrupt input must be configured to an available rpx pin. see section 9.4 ?peripheral pin select? for more information.
? 2007 microchip technology inc. preliminary ds39881b-page 67 pic24fj64ga004 family register 6-12: iec2: interrupt enable control register 2 u-0 u-0 r/w -0 u-0 u-0 u-0 r/w -0 u-0 ? ?pmpie ? ? ?oc5ie ? bit 15 bit 8 r/w -0 r/w -0 r/w -0 u-0 u-0 u-0 r/w -0 r/w -0 ic5ie ic4ie ic3ie ? ? ? spi2ie spf2ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 pmpie: parallel master port interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 12-10 unimplemented: read as ? 0 ? bit 9 oc5ie: output compare channel 5 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 8 unimplemented: read as ? 0 ? bit 7 ic5ie: input capture channel 5 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 6 ic4ie: input capture channel 4 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 5 ic3ie: input capture channel 3 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 4-2 unimplemented: read as ? 0 ? bit 1 spi2ie: spi2 event interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 0 spf2ie: spi2 fault interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled
pic24fj64ga004 family ds39881b-page 68 preliminary ? 2007 microchip technology inc. register 6-13: iec3: interrupt enable control register 3 u-0 r/w -0 u-0 u-0 u-0 u-0 u-0 u-0 ?rtcie ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w -0 r/w -0 u-0 ? ? ? ? ? mi2c2ie si2c2ie ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14 rtcie: real-time clock/calendar interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 13-3 unimplemented: read as ? 0 ? bit 2 mi2c2ie: master i2c2 event interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 1 si2c2ie: slave i2c2 event interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 0 unimplemented: read as ? 0 ?
? 2007 microchip technology inc. preliminary ds39881b-page 69 pic24fj64ga004 family register 6-14: iec4: interrupt enable control register 4 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w -0 ? ? ? ? ? ? ?lvdie bit 15 bit 8 u-0 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 u-0 ? ? ? ? crcie u2erie u1erie ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-9 unimplemented: read as ? 0 ? bit 8 lvdie: low-voltage detect interrupt enable status bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 7-4 unimplemented: read as ? 0 ? bit 3 crcie: crc generator interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 2 u2erie: uart2 error interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 1 u1erie: uart1 error interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 0 unimplemented: read as ? 0 ?
pic24fj64ga004 family ds39881b-page 70 preliminary ? 2007 microchip technology inc. register 6-15: ipc0: interrupt priority control register 0 u-0 r/w -1 r/w -0 r/w -0 u-0 r/w -1 r/w -0 r/w -0 ? t1ip2 t1ip1 t1ip0 ? oc1ip2 oc1ip1 oc1ip0 bit 15 bit 8 u-0 r/w -1 r/w -0 r/w -0 u-0 r/w -1 r/w -0 r/w -0 ? ic1ip2 ic1ip1 ic1ip0 ? int0ip2 int0ip1 int0ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 t1ip2:t1ip0: timer1 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 oc1ip2:oc1ip0: output compare channel 1 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 ic1ip2:ic1ip0: input capture channel 1 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 int0ip2:int0ip0: external interrupt 0 priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
? 2007 microchip technology inc. preliminary ds39881b-page 71 pic24fj64ga004 family register 6-16: ipc1: interrupt priority control register 1 u-0 r/w -1 r/w -0 r/w -0 u-0 r/w -1 r/w -0 r/w -0 ? t2ip2 t2ip1 t2ip0 ? oc2ip2 oc2ip1 oc2ip0 bit 15 bit 8 u-0 r/w -1 r/w -0 r/w -0 u-0 u-0 u-0 u-0 ? ic2ip2 ic2ip1 ic2ip0 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 t2ip2:t2ip0: timer2 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 oc2ip2:oc2ip0: output compare channel 2 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 ic2ip2:ic2ip0: input capture channel 2 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ?
pic24fj64ga004 family ds39881b-page 72 preliminary ? 2007 microchip technology inc. register 6-17: ipc2: interrupt priority control register 2 u-0 r/w -1 r/w -0 r/w -0 u-0 r/w -1 r/w -0 r/w -0 ? u1rxip2 u1rxip1 u1rxip0 ? spi1ip2 spi1ip1 spi1ip0 bit 15 bit 8 u-0 r/w -1 r/w -0 r/w -0 u-0 r/w -1 r/w -0 r/w -0 ? spf1ip2 spf1ip1 spf1ip0 ? t3ip2 t3ip1 t3ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 u1rxip2:u1rxip0: uart1 receiver interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 spi1ip2:spi1ip0: spi1 event interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 spf1ip2:spf1ip0: spi1 fault interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 t3ip2:t3ip0: timer3 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
? 2007 microchip technology inc. preliminary ds39881b-page 73 pic24fj64ga004 family register 6-18: ipc3: interrupt priority control register 3 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w -1 r/w -0 r/w -0 u-0 r/w -1 r/w -0 r/w -0 ? ad1ip2 ad1ip1 ad1ip0 ? u1txip2 u1txip1 u1txip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-4 ad1ip2:ad1ip0: a/d conversion complete interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 u1txip2:u1txip0: uart1 transmitter interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
pic24fj64ga004 family ds39881b-page 74 preliminary ? 2007 microchip technology inc. register 6-19: ipc4: interrupt priority control register 4 u-0 r/w -1 r/w -0 r/w -0 u-0 r/w -1 r/w -0 r/w -0 ? cnip2 cnip1 cnip0 ? cmip2 cmip1 cmip0 bit 15 bit 8 u-0 r/w -1 r/w -0 r/w -0 u-0 r/w -1 r/w -0 r/w -0 ? mi2c1p2 mi2c1p1 mi2c1p0 ? si2c1p2 si2c1p1 si2c1p0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 cnip2:cnip0: input change notification interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 cmip2:cmip0: comparator interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 mi2c1p2:mi2c1p0: master i2c1 event interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 si2c1p2:si2c1p0: slave i2c1 event interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
? 2007 microchip technology inc. preliminary ds39881b-page 75 pic24fj64ga004 family register 6-20: ipc5: interrupt priority control register 5 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w -1 r/w -0 r/w -0 ? ? ? ? ? int1ip2 int1ip1 int1ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-3 unimplemented: read as ? 0 ? bit 2-0 int1ip2:int1ip0: external interrupt 1 priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
pic24fj64ga004 family ds39881b-page 76 preliminary ? 2007 microchip technology inc. register 6-21: ipc6: interrupt priority control register 6 u-0 r/w -1 r/w -0 r/w -0 u-0 r/w -1 r/w -0 r/w -0 ? t4ip2 t4ip1 t4ip0 ? oc4ip2 oc4ip1 oc4ip0 bit 15 bit 8 u-0 r/w -1 r/w -0 r/w -0 u-0 u-0 u-0 u-0 ? oc3ip2 oc3ip1 oc3ip0 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 t4ip2:t4ip0: timer4 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 oc4ip2:oc4ip0: output compare channel 4 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 oc3ip2:oc3ip0: output compare channel 3 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ?
? 2007 microchip technology inc. preliminary ds39881b-page 77 pic24fj64ga004 family register 6-22: ipc7: interrupt priority control register 7 u-0 r/w -1 r/w -0 r/w -0 u-0 r/w -1 r/w -0 r/w -0 ? u2txip2 u2txip1 u2txip0 ? u2rxip2 u2rxip1 u2rxip0 bit 15 bit 8 u-0 r/w -1 r/w -0 r/w -0 u-0 r/w -1 r/w -0 r/w -0 ? int2ip2 int2ip1 int2ip0 ? t5ip2 t5ip1 t5ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 u2txip2:u2txip0: uart2 transmitter interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 u2rxip2:u2rxip0: uart2 receiver interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 int2ip2:int2ip0: external interrupt 2 priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 t5ip2:t5ip0: timer5 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
pic24fj64ga004 family ds39881b-page 78 preliminary ? 2007 microchip technology inc. register 6-23: ipc8: interrupt priority control register 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w -1 r/w -0 r/w -0 u-0 r/w -1 r/w -0 r/w -0 ? spi2ip2 spi2ip1 spi2ip0 ? spf2ip2 spf2ip1 spf2ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-4 spi2ip2:spi2ip0: spi2 event interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 spf2ip2:spf2ip0: spi2 fault interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
? 2007 microchip technology inc. preliminary ds39881b-page 79 pic24fj64ga004 family register 6-24: ipc9: interrupt priority control register 9 u-0 r/w -1 r/w -0 r/w -0 u-0 r/w -1 r/w -0 r/w -0 ? ic5ip2 ic5ip1 ic5ip0 ? ic4ip2 ic4ip1 ic4ip0 bit 15 bit 8 u-0 r/w -1 r/w -0 r/w -0 u-0 u-0 u-0 u-0 ? ic3ip2 ic3ip1 ic3ip0 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 ic5ip2:ic5ip0: input capture channel 5 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 ic4ip2:ic4ip0: input capture channel 4 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 ic3ip2:ic3ip0: input capture channel 3 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ?
pic24fj64ga004 family ds39881b-page 80 preliminary ? 2007 microchip technology inc. register 6-25: ipc10: interrupt priority control register 10 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w -1 r/w -0 r/w -0 u-0 u-0 u-0 u-0 ? oc5ip2 oc5ip1 oc5ip0 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-4 oc5ip2:oc5ip0: output compare channel 5 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ? register 6-26: ipc11: interrupt priority control register 11 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w -1 r/w -0 r/w -0 u-0 u-0 u-0 u-0 ? pmpip2 pmpip1 pmpip0 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-4 pmpip2:pmpip0: parallel master port interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ?
? 2007 microchip technology inc. preliminary ds39881b-page 81 pic24fj64ga004 family register 6-27: ipc12: interrupt priority control register 12 u-0 u-0 u-0 u-0 u-0 r/w -1 r/w -0 r/w -0 ? ? ? ? ? mi2c2p2 mi2c2p1 mi2c2p0 bit 15 bit 8 u-0 r/w -1 r/w -0 r/w -0 u-0 u-0 u-0 u-0 ? si2c2p2 si2c2p1 si2c2p0 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 10-8 mi2c2p2:mi2c2p0: master i2c2 event interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 si2c2p2:si2c2p0: slave i2c2 event interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ?
pic24fj64ga004 family ds39881b-page 82 preliminary ? 2007 microchip technology inc. register 6-28: ipc15: interrupt priority control register 15 u-0 u-0 u-0 u-0 u-0 r/w -1 r/w -0 r/w -0 ? ? ? ? ? rtcip2 rtcip1 rtcip0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 10-8 rtcip2:rtcip0: real-time clock/calendar interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7-0 unimplemented: read as ? 0 ?
? 2007 microchip technology inc. preliminary ds39881b-page 83 pic24fj64ga004 family register 6-29: ipc16: interrupt priority control register 16 u-0 r/w -1 r/w -0 r/w -0 u-0 r/w -1 r/w -0 r/w -0 ? crcip2 crcip1 crcip0 ? u2erip2 u2erip1 u2erip0 bit 15 bit 8 u-0 r/w -1 r/w -0 r/w -0 u-0 u-0 u-0 u-0 ? u1erip2 u1erip1 u1erip0 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 crcip2:crcip0: crc generator error interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 u2erip2:u2erip0: uart2 error interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 u1erip2:u1erip0: uart1 error interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ?
pic24fj64ga004 family ds39881b-page 84 preliminary ? 2007 microchip technology inc. register 6-30: ipc18: interrupt priority control register 18 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w -1 r/w -0 r/w -0 ? ? ? ? ? lvdip2 lvdip1 lvdip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-3 unimplemented: read as ? 0 ? bit 12-0 lvdip2:lvdip0: low-voltage detect interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
? 2007 microchip technology inc. preliminary ds39881b-page 85 pic24fj64ga004 family 6.4 interrupt setup procedures 6.4.1 initialization to configure an interrupt source: 1. set the nstdis control bit (intcon1<15>) if nested interrupts are not desired. 2. select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate ipcx register. the priority level will depend on the specific application and type of interrupt source. if multiple priority levels are not desired, the ipcx register control bits for all enabled interrupt sources may be programmed to the same non-zero value. 3. clear the interrupt flag status bit associated with the peripheral in the associated ifsx register. 4. enable the interrupt source by setting the interrupt enable control bit associated with the source in the appropriate iecx register. 6.4.2 interrupt service routine the method that is used to declare an isr and initialize the ivt with the correct vector address will depend on the programming language (i.e., ?c? or assembler) and the language development toolsuite that is used to develop the application. in general, the user must clear the interrupt flag in the appropriate ifsx register for the source of the interrupt that the isr handles. otherwise, the isr will be re-entered immediately after exiting the routine. if the isr is coded in assembly language, it must be terminated using a retfie instruction to unstack the saved pc value, srl value and old cpu priority level. 6.4.3 trap service routine a trap service routine (tsr) is coded like an isr, except that the appropriate trap status flag in the intcon1 register must be cleared to avoid re-entry into the tsr. 6.4.4 interrupt disable all user interrupts can be disabled using the following procedure: 1. push the current sr value onto the software stack using the push instruction. 2. force the cpu to priority level 7 by inclusive oring the value oeh with srl. to enable user interrupts, the pop instruction may be used to restore the previous sr value. note that only user interrupts with a priority level of 7 or less can be disabled. trap sources (level 8-15) cannot be disabled. the disi instruction provides a convenient way to disable interrupts of priority levels 1-6 for a fixed period of time. level 7 interrupt sources are not disabled by the disi instruction. note: at a device reset, the ipcx registers are initialized, such that all user interrupt sources are assigned to priority level 4.
pic24fj64ga004 family ds39881b-page 86 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds39881b-page 87 pic24fj64ga004 family 7.0 oscillator configuration the oscillator system for pic24fj64ga004 family devices has the following features: ? a total of four external and internal oscillator options as clock sources, providing 11 different clock modes ? on-chip 4x pll to boost internal operating frequency on select internal and external oscillator sources ? software-controllable switching between various clock sources ? software-controllable postscaler for selective clocking of cpu for system power savings ? a fail-safe clock monitor (fscm) that detects clock failure and permits safe application recovery or shutdown a simplified diagram of the oscillator system is shown in figure 7-1. figure 7-1: pic24fj64ga004 family clock diagram note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the associated ?pic24f family reference manual? chapter. pic24fj64ga004 family secondary oscillator soscen enable oscillator sosco sosci clock source option for other modules osci osco primary oscillator xt, hs, ec cpu peripherals postscaler clkdiv<10:8> wdt, pwrt 8 mhz frcdiv 31 khz (nominal) frc oscillator lprc oscillator sosc lprc postscaler clock control logic fail-safe clock monitor clkdiv<14:12> frc clko (nominal) 4 x pll xtpll, hspll ecpll,frcpll 8 mhz 4 mhz
pic24fj64ga004 family ds39881b-page 88 preliminary ? 2007 microchip technology inc. 7.1 cpu clocking scheme the system clock source can be provided by one of four sources: ? primary oscillator (posc) on the osci and osco pins ? secondary oscillator (sosc) on the sosci and sosco pins ? fast internal rc (frc) oscillator ? low-power internal rc (lprc) oscillator the primary oscillator and frc sources have the option of using the internal 4x pll. the frequency of the frc clock source can optionally be reduced by the programmable clock divider. the selected clock source generates the processor and peripheral clock sources. the processor clock source is divided by two to pro- duce the internal instruction cycle clock, f cy . in this document, the instruction cycle clock is also denoted by f osc /2. the internal instruction cycle clock, f osc /2, can be provided on the osco i/o pin for some operating modes of the primary oscillator. 7.2 oscillator configuration the oscillator source (and operating mode) that is used at a device power-on reset event is selected using configuration bit settings. the oscillator config- uration bit settings are located in the configuration registers in the program memory (refer to section 23.1 ?configuration bits? for further details). the primary oscillator configuration bits, poscmd1:poscmd0 (configuration word 2<1:0>), and the initial oscillator select configuration bits, fnosc2:fnosc0 (configuration word 2<10:8>), select the oscillator source that is used at a power-on reset. the frc primary oscillator with postscaler (frcdiv) is the default (unprogrammed) selection. the secondary oscillator, or one of the internal oscillators, may be chosen by programming these bit locations. the configuration bits allow users to choose between the various clock modes, shown in table 7-1. 7.2.1 clock switching mode configuration bits the fcksm configuration bits (configuration word 2<7:6>) are used to jointly configure device clock switching and the fail-safe clock monitor (fscm). clock switching is enabled only when fcksm1 is programmed (? 0 ?). the fscm is enabled only when fcksm1:fcksm0 are both programmed (? 00 ?). table 7-1: configuration bit va lues for clock selection oscillator mode oscillator source poscmd1: poscmd0 fnosc2: fnosc0 note fast rc oscillator with postscaler (frcdiv) internal 00 111 1, 2 (reserved) internal 00 110 1 low-power rc oscillator (lprc) internal 00 101 1 secondary (timer1) oscillator (sosc) secondary 00 100 1 primary oscillator (xt) with pll module (xtpll) primary 01 011 primary oscillator (ec) with pll module (ecpll) primary 00 011 primary oscillator (hs) primary 10 010 primary oscillator (xt) primary 01 010 primary oscillator (ec) primary 00 010 fast rc oscillator with pll module (frcpll) internal 00 001 1 fast rc oscillator (frc) internal 00 000 1 note 1: osco pin function is determined by the osciofcn configuration bit. 2: this is the default oscillator mode for an unprogrammed (erased) device.
? 2007 microchip technology inc. preliminary ds39881b-page 89 pic24fj64ga004 family 7.3 control registers the operation of the oscillator is controlled by three special function registers: ? osccon ?clkdiv ?osctun the osccon register (register 7-1) is the main con- trol register for the oscillator. it controls clock source switching and allows the monitoring of clock sources. the clock divider register (register 7-2) controls the features associated with doze mode, as well as the postscaler for the frc oscillator. the frc oscillator tune register (register 7-3) allows the user to fine tune the frc oscillator over a range of approximately 12%. each bit increment or decrement changes the factory calibrated frequency of the frc oscillator by a fixed amount.
pic24fj64ga004 family ds39881b-page 90 preliminary ? 2007 microchip technology inc. register 7-1: osccon: oscillator control register u-0 r-0 r-0 r-0 u-0 r/w -x (1) r/w -x (1) r/w -x (1) ? cosc2 cosc1 cosc0 ? nosc2 nosc1 nosc0 bit 15 bit 8 r/so-0 r/w -0 r-0 (3) u-0 r/co-0 u-0 r/w -0 r/w -0 clklock iolock (2) lock ?cf ? soscen oswen bit 7 bit 0 legend: co = clear-only bit so = set-only bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 cosc2:cosc0: current oscillator selection bits 111 = fast rc oscillator with postscaler (frcdiv) 110 = reserved 101 = low-power rc oscillator (lprc) 100 = secondary oscillator (sosc) 011 = primary oscillator with pll module (xtpll, hspll, ecpll) 010 = primary oscillator (xt, hs, ec) 001 = fast rc oscillator with postscaler and pll module (frcpll) 000 = fast rc oscillator (frc) bit 11 unimplemented: read as ? 0 ? bit 10-8 nosc2:nosc0: new oscillator selection bits (1) 111 = fast rc oscillator with postscaler (frcdiv) 110 = reserved 101 = low-power rc oscillator (lprc) 100 = secondary oscillator (sosc) 011 = primary oscillator with pll module (xtpll, hspll, ecpll) 010 = primary oscillator (xt, hs, ec) 001 = fast rc oscillator with postscaler and pll module (frcpll) 000 = fast rc oscillator (frc) bit 7 clklock: clock selection lock enabled bit if fscm is enabled (fcksm1 = 1 ): 1 = clock and pll selections are locked 0 = clock and pll selections are not locked and may be modified by setting the oswen bit if fscm is disabled (fcksm1 = 0 ): clock and pll selections are never locked and may be modified by setting the oswen bit. bit 6 iolock: i/o lock enable bit (2) 1 = i/o lock is active 0 = i/o lock is not active bit 5 lock: pll lock status bit (3) 1 = pll module is in lock or pll module start-up timer is satisfied 0 = pll module is out of lock, pll start-up timer is running or pll is disabled bit 4 unimplemented: read as ? 0 ? note 1: reset values for these bits are determined by the fnosc configuration bits. 2: the state of the iolock bit can only be changed once an unlocking sequence has been executed. in addition, if the iol1way configuration bit is ? 1 ?, once the iolock bit is set, it cannot be cleared. 3: also resets to ? 0 ? during any valid clock switch or whenever a non-pll clock mode is selected.
? 2007 microchip technology inc. preliminary ds39881b-page 91 pic24fj64ga004 family bit 3 cf: clock fail detect bit 1 = fscm has detected a clock failure 0 = no clock failure has been detected bit 2 unimplemented: read as ? 0 ? bit 1 soscen: 32 khz secondary oscillator (sosc) enable bit 1 = enable secondary oscillator 0 = disable secondary oscillator bit 0 oswen: oscillator switch enable bit 1 = initiate an oscillator switch to clock source specified by nosc2:nosc0 bits 0 = oscillator switch is complete register 7-1: osccon: oscillator control register (continued) note 1: reset values for these bits are determined by the fnosc configuration bits. 2: the state of the iolock bit can only be changed once an unlocking sequence has been executed. in addition, if the iol1way configuration bit is ? 1 ?, once the iolock bit is set, it cannot be cleared. 3: also resets to ? 0 ? during any valid clock switch or whenever a non-pll clock mode is selected.
pic24fj64ga004 family ds39881b-page 92 preliminary ? 2007 microchip technology inc. register 7-2: clkdiv: clock divider register r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -1 roi doze2 doze1 doze0 dozen (1) rcdiv2 rcdiv1 rcdiv0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 roi: recover on interrupt bit 1 = interrupts clear the dozen bit and reset the cpu peripheral clock ratio to 1:1 0 = interrupts have no effect on the dozen bit bit 14-12 doze2:doze0: cpu peripheral clock ratio select bits 111 = 1:128 110 = 1:64 101 = 1:32 100 = 1:16 011 = 1:8 010 = 1:4 001 = 1:2 000 = 1:1 bit 11 dozen: doze enable bit (1) 1 = doze2:doze0 bits specify the cpu peripheral clock ratio 0 = cpu peripheral clock ratio set to 1:1 bit 10-8 rcdiv2:rcdiv0: frc postscaler select bits 111 = 31.25 khz (divide by 256) 110 = 125 khz (divide by 64) 101 = 250 khz (divide by 32) 100 = 500 khz (divide by 16) 011 = 1 mhz (divide by 8) 010 = 2 mhz (divide by 4) 001 = 4 mhz (divide by 2) 000 = 8 mhz (divide by 1) bit 7-0 unimplemented: read as ? 0 ? note 1: this bit is automatically cleared when the roi bit is set and an interrupt occurs.
? 2007 microchip technology inc. preliminary ds39881b-page 93 pic24fj64ga004 family 7.4 clock switching operation with few limitations, applications are free to switch between any of the four clock sources (posc, sosc, frc and lprc) under software control and at any time. to limit the possible side effects that could result from this flexibility, pic24f devices have a safeguard lock built into the switching process. 7.4.1 enabling clock switching to enable clock switching, the fcksm1 configuration bit in flash configuration word 2 must be programmed to ? 0 ?. (refer to section 23.1 ?configuration bits? for further details.) if the fcksm1 configuration bit is unprogrammed (? 1 ?), the clock switching function and fail-safe clock monitor function are disabled. this is the default setting. the noscx control bits (osccon<10:8>) do not control the clock selection when clock switching is dis- abled. however, the coscx bits (osccon<14:12>) will reflect the clock source selected by the fnoscx configuration bits. the oswen control bit (osccon<0>) has no effect when clock switching is disabled. it is held at ? 0 ? at all times. register 7-3: osctun: frc oscillator tune register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? tun5 tun4 tun3 tun2 tun1 tun0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as ? 0 ? bit 5-0 tun5:tun0: frc oscillator tuning bits 011111 = maximum frequency deviation 011110 = ? ? ? 000001 = 000000 = center frequency, oscillator is running at factory calibrated frequency 111111 = ? ? ? 100001 = 100000 = minimum frequency deviation note: the primary oscillator mode has three different submodes (xt, hs and ec) which are determined by the poscmdx configuration bits. while an application can switch to and from primary oscillator mode in software, it cannot switch between the different primary submodes without reprogramming the device.
pic24fj64ga004 family ds39881b-page 94 preliminary ? 2007 microchip technology inc. 7.4.2 oscillator switching sequence at a minimum, performing a clock switch requires this basic sequence: 1. if desired, read the coscx bits (osccon<14:12>), to determine the current oscillator source. 2. perform the unlock sequence to allow a write to the osccon register high byte. 3. write the appropriate value to the noscx bits (osccon<10:8>) for the new oscillator source. 4. perform the unlock sequence to allow a write to the osccon register low byte. 5. set the oswen bit to initiate the oscillator switch. once the basic sequence is completed, the system clock hardware responds automatically as follows: 1. the clock switching hardware compares the coscx bits with the new value of the noscx bits. if they are the same, then the clock switch is a redundant operation. in this case, the oswen bit is cleared automatically and the clock switch is aborted. 2. if a valid clock switch has been initiated, the lock (osccon<5>) and cf (osccon<3>) bits are cleared. 3. the new oscillator is turned on by the hardware if it is not currently running. if a crystal oscillator must be turned on, the hardware will wait until the ost expires. if the new source is using the pll, then the hardware waits until a pll lock is detected (lock = 1 ). 4. the hardware waits for 10 clock cycles from the new clock source and then performs the clock switch. 5. the hardware clears the oswen bit to indicate a successful clock transition. in addition, the noscx bit values are transferred to the coscx bits. 6. the old clock source is turned off at this time, with the exception of lprc (if wdt or fscm are enabled) or sosc (if soscen remains set). a recommended code sequence for a clock switch includes the following: 1. disable interrupts during the osccon register unlock and write sequence. 2. execute the unlock sequence for the osccon high byte by writing 78h and 9ah to osccon<15:8> in two back-to-back instructions. 3. write new oscillator source to the noscx bits in the instruction immediately following the unlock sequence. 4. execute the unlock sequence for the osccon low byte by writing 46h and 57h to osccon<7:0> in two back-to-back instructions. 5. set the oswen bit in the instruction immediately following the unlock sequence. 6. continue to execute code that is not clock sensitive (optional). 7. invoke an appropriate amount of software delay (cycle counting) to allow the selected oscillator and/or pll to start and stabilize. 8. check to see if oswen is ? 0 ?. if it is, the switch was successful. if oswen is still set, then check the lock bit to determine the cause of failure. the core sequence for unlocking the osccon register and initiating a clock switch is shown in example 7-1. example 7-1: basic code sequence for clock switching note 1: the processor will continue to execute code throughout the clock switching sequence. timing sensitive code should not be executed during this time. 2: direct clock switches between any primary oscillator mode with pll and frcpll mode are not permitted. this applies to clock switches in either direc- tion. in these instances, the application must switch to frc mode as a transition clock source between the two pll modes. ;place the new oscillator selection in w0 ;oscconh (high byte) unlock sequence mov #oscconh, w1 mov #0x78, w2 mov #0x9a, w3 mov.b w2, [w1] mov.b w3, [w1] ;set new oscillator selection mov.b wreg, oscconh ;oscconl (low byte) unlock sequence mov #oscconl, w1 mov #0x46, w2 mov #0x57, w3 mov.b w2, [w1] mov.b w3, [w1] ;start oscillator switch operation bset osccon,#0
? 2007 microchip technology inc. preliminary ds39881b-page 95 pic24fj64ga004 family 8.0 power-saving features the pic24fj64ga004 family of devices provides the ability to manage power consumption by selectively managing clocking to the cpu and the peripherals. in general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. all pic24f devices manage power consumption in four different ways: ? clock frequency ? instruction-based sleep and idle modes ? software controlled doze mode ? selective peripheral control in software combinations of these methods can be used to selec- tively tailor an application?s power consumption, while still maintaining critical application features, such as timing-sensitive communications. 8.1 clock frequency and clock switching pic24f devices allow for a wide range of clock frequencies to be selected under application control. if the system clock configuratio n is not locked, users can choose low-power or high-precision oscillators by simply changing the nosc bits. the process of changing a sys- tem clock during operation, as well as limitations to the process, are discussed in more detail in section 7.0 ?oscillator configuration? . 8.2 instruction-based power-saving modes pic24f devices have two special power-saving modes that are entered through the execution of a special pwrsav instruction. sleep mode stops clock operation and halts all code execution; idle mode halts the cpu and code execution, but allows peripheral modules to continue operation. the assembly syntax of the pwrsav instruction is shown in example 8-1. sleep and idle modes can be exited as a result of an enabled interrupt, wdt time-out or a device reset. when the device exits these modes, it is said to ?wake-up?. 8.2.1 sleep mode sleep mode has these features: ? the system clock source is shut down. if an on-chip oscillator is used, it is turned off. ? the device current consumption will be reduced to a minimum provided that no i/o pin is sourcing current. ? the fail-safe clock monitor does not operate during sleep mode since the system clock source is disabled. ? the lprc clock will continue to run in sleep mode if the wdt is enabled. ? the wdt, if enabled, is automatically cleared prior to entering sleep mode. ? some device features or peripherals may continue to operate in sleep mode. this includes items such as the input change notification on the i/o ports, or peripherals that use an external clock input. any peripheral that requires the system clock source for its operation will be disabled in sleep mode. the device will wake-up from sleep mode on any of the these events: ? on any interrupt source that is individually enabled ? on any form of device reset ? on a wdt time-out on wake-up from sleep, the processor will restart with the same clock source that was active when sleep mode was entered. example 8-1: pwrsav instruction syntax note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the associated ?pic24f family reference manual? chapter. note: sleep_mode and idle_mode are con- stants defined in the assembler include file for the selected device. pwrsav #sleep_mode ; put the device into sleep mode pwrsav #idle_mode ; put the device into idle mode
pic24fj64ga004 family ds39881b-page 96 preliminary ? 2007 microchip technology inc. 8.2.2 idle mode idle mode has these features: ? the cpu will stop executing instructions. ? the wdt is automatically cleared. ? the system clock source remains active. by default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see section 8.4 ?selective peripheral module control? ). ? if the wdt or fscm is enabled, the lprc will also remain active. the device will wake from idle mode on any of these events: ? any interrupt that is individually enabled. ? any device reset. ? a wdt time-out. on wake-up from idle, the clock is re-applied to the cpu and instruction execution begins immediately, starting with the instruction following the pwrsav instruction or the first instruction in the isr. 8.2.3 interrupts coincident with power save instructions any interrupt that coincides with the execution of a pwrsav instruction will be held off until entry into sleep or idle mode has completed. the device will then wake-up from sleep or idle mode. 8.3 doze mode generally, changing clock speed and invoking one of the power-saving modes are the preferred strategies for reducing power consumption. there may be cir- cumstances, however, where this is not practical. for example, it may be necessary for an application to maintain uninterrupted synchronous communication, even while it is doing nothing else. reducing system clock speed may introduce communication errors, while using a power-saving mode may stop communications completely. doze mode is a simple and effective alternative method to reduce power consumption while the device is still executing code. in this mode, the system clock contin- ues to operate from the same source and at the same speed. peripheral modules continue to be clocked at the same speed while the cpu clock speed is reduced. synchronization between the two clock domains is maintained, allowing the peripherals to access the sfrs while the cpu executes code at a slower rate. doze mode is enabled by setting the dozen bit (clkdiv<11>). the ratio between peripheral and core clock speed is determined by the doze2:doze0 bits (clkdiv<14:12>). there are eight possible configurations, from 1:1 to 1:256, with 1:1 being the default. it is also possible to use doze mode to selectively reduce power consumption in event driven applica- tions. this allows clock sensitive functions, such as synchronous communications, to continue without interruption while the cpu idles, waiting for something to invoke an interrupt routine. enabling the automatic return to full-speed cpu operation on interrupts is enabled by setting the roi bit (clkdiv<15>). by default, interrupt events have no effect on doze mode operation. 8.4 selective peripheral module control idle and doze modes allow users to substantially reduce power consumption by slowing or stopping the cpu clock. even so, peripheral modules still remain clocked and thus consume power. there may be cases where the application needs what these modes do not provide: the allocation of power resources to cpu processing with minimal power consumption from the peripherals. pic24f devices address this requirement by allowing peripheral modules to be selectively disabled, reducing or eliminating their power consumption. this can be done with two control bits: ? the peripheral enable bit, generically named, ?xxxen?, located in the module?s main control sfr. ? the peripheral module disable (pmd) bit, generically named, ?xxxmd?, located in one of the pmd control registers. both bits have similar functions in enabling or disabling its associated module. setting the pmd bit for a module disables all clock sources to that module, reducing its power consumption to an absolute minimum. in this state, the control and status registers associated with the peripheral will also be disabled, so writes to those registers will have no effect and read values will be invalid. many peripheral modules have a corresponding pmd bit. in contrast, disabling a module by clearing its xxxen bit disables its functionality, but leaves its registers available to be read and written to. power consumption is reduced, but not by as much as the pmd bit does. most peripheral modules have an enable bit; exceptions include capture, compare and rtcc. to achieve more selective power savings, peripheral modules can also be selectively disabled when the device enters idle mode. this is done through the control bit of the generic name format, ?xxxidl?. by default, all modules that can operate during idle mode will do so. using the disable on idle feature allows fur- ther reduction of power consumption during idle mode, enhancing power savings for extremely critical power applications.
? 2007 microchip technology inc. preliminary ds39881b-page 97 pic24fj64ga004 family 9.0 i/o ports all of the device pins (except v dd , v ss , mclr and osci/clki) are shared between the peripherals and the parallel i/o ports. all i/o input ports feature schmitt trigger inputs for improved noise immunity. 9.1 parallel i/o (pio) ports a parallel i/o port that shares a pin with a peripheral is, in general, subservient to the peripheral. the periph- eral?s output buffer data and control signals are provided to a pair of multiplexers. the multiplexers select whether the peripheral or the associated port has ownership of the output data and control signals of the i/o pin. the logic also prevents ?loop through?, in which a port?s digital output can drive the input of a peripheral that shares the same pin. figure 9-1 shows how ports are shared with other peripherals and the associated i/o pin to which they are connected. when a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. the i/o pin may be read, but the output driver for the parallel port bit will be disabled. if a peripheral is enabled, but the peripheral is not actively driving a pin, that pin may be driven by a port. all port pins have three registers directly associated with their operation as digital i/o. the data direction register (trisx) determines whether the pin is an input or an output. if the data direction bit is a ? 1 ?, then the pin is an input. all port pins are defined as inputs after a reset. reads from the output latch register (latx), read the latch. writes to the latch, write the latch. reads from the port (portx), read the port pins, while writes to the port pins, write the latch. any bit and its associated data and control registers that are not valid for a particular device will be disabled. that means the corresponding latx and trisx registers and the port pin will read as zeros. when a pin is shared with another peripheral or func- tion that is defined as an input only, it is, nevertheless, regarded as a dedicated port because there is no other competing source of outputs. figure 9-1: block diagram of a typical shared port structure note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the associated ?pic24f family reference manual? chapter. q d ck wr lat + tris latch i/o pin wr port data bus q d ck data latch read port read tris 1 0 1 0 wr tris peripheral output data output enable peripheral input data i/o peripheral module peripheral output enable pio module output multiplexers output data input data peripheral module enable read lat
pic24fj64ga004 family ds39881b-page 98 preliminary ? 2007 microchip technology inc. 9.1.1 open-drain configuration in addition to the port, lat and tris registers for data control, each port pin can also be individually con- figured for either digital or open-drain output. this is controlled by the open-drain control register, odcx, associated with each port. setting any of the bits con- figures the corresponding pin to act as an open-drain output. the open-drain feature allows the generation of outputs higher than v dd (e.g., 5v) on any desired digital only pins by using external pull-up resistors. the maximum open-drain voltage allowed is the same as the maximum v ih specification. 9.2 configuring analog port pins the use of the ad1pcfg and tris registers control the operation of the a/d port pins. the port pins that are desired as analog inputs must have their correspond- ing tris bit set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. when reading the port register, all pins configured as analog input channels will read as cleared (a low level). pins configured as digital inputs will not convert an analog input. analog levels on any pin that is defined as a digital input (including the anx pins) may cause the input buffer to consume current that exceeds the device specifications. 9.2.1 i/o port write/read timing one instruction cycle is required between a port direction change or port write operation and a read operation of the same port. typically, this instruction would be a nop . 9.3 input change notification the input change notification function of the i/o ports allows the pic24fj64ga004 family of devices to gen- erate interrupt requests to the processor in response to a change of state on selected input pins. this feature is capable of detecting input change of states even in sleep mode, when the clocks are disabled. depending on the device pin count, there are up to 22 external sig- nals (cn0 through cn21) that may be selected (enabled) for generating an interrupt request on a change of state. there are four control registers associated with the cn module. the cnen1 and cnen2 registers contain the interrupt enable control bits for each of the cn input pins. setting any of these bits enables a cn interrupt for the corresponding pins. each cn pin also has a weak pull-up connected to it. the pull-ups act as a current source that is connected to the pin, and eliminate the need for external resistors when push button or keypad devices are connected. the pull-ups are enabled separately using the cnpu1 and cnpu2 registers, which contain the control bits for each of the cn pins. setting any of the control bits enables the weak pull-ups for the corresponding pins. when the internal pull-up is selected, the pin uses v ddcore as the pull-up source voltage. make sure that there is no external pull-up source when the internal pull-ups are enabled, as the voltage difference can cause a current path. example 9-1: port write/read example note: pull-ups on change notification pins should always be disabled whenever the port pin is configured as a digital output. mov 0xff00, w0 ; configure portb<15:8> as inputs mov w0, trisbb ; and portb<7:0> as outputs nop ; delay 1 cycle btss portb, #13 ; next instruction
? 2007 microchip technology inc. preliminary ds39881b-page 99 pic24fj64ga004 family 9.4 peripheral pin select a major challenge in general purpose devices is provid- ing the largest possible set of peripheral features while minimizing the conflict of features on i/o pins. the chal- lenge is even greater on low pin count devices similar to the pic24fj64ga family. in an application that needs to use more than one peripheral multiplexed on single pin, inconvenient workarounds in application code or a complete redesign may be the only option. the peripheral pin select feature provides an alterna- tive to these choices by enabling the user?s peripheral set selection and their placement on a wide range of i/o pins. by increasing the pinout options available on a particular device, users can better tailor the microcontroller to their entire application, rather than trimming the application to fit the device. the peripheral pin select feature operates over a fixed subset of digital i/o pins. users may independently map the input and/or output of any one of many digital peripherals to any one of these i/o pins. peripheral pin select is performed in software and generally does not require the device to be reprogrammed. hardware safeguards are included that prevent accidental or spurious changes to the peripheral mapping once it has been established. 9.4.1 available pins the peripheral pin select feature is used with a range of up to 26 pins; the number of available pins is depen- dent on the particular device and its pincount. pins that support the peripheral pin select feature include the designation ?rpn? in their full pin designation, where ?rp? designates a remappable peripheral and ?n? is the remappable pin number. see table 1-2 for pinout options in each package offering. 9.4.2 available peripherals the peripherals managed by the peripheral pin select are all digital only peripherals. these include general serial communications (uart and spi), general pur- pose timer clock inputs, timer-related peripherals (input capture and output compare) and external interrupt inputs. also included are the outputs of the comparator module, since these are discrete digital signals. the peripheral pin select module is not applied to i 2 c?, change notification inputs, rtcc alarm outputs or peripherals with analog inputs. a key difference between pin select and non pin select peripherals is that pin select peripherals are not asso- ciated with a default i/o pin. the peripheral must always be assigned to a specific i/o pin before it can be used. in contrast, non pin select peripherals are always available on a default pin, assuming that the peripheral is active and not conflicting with another peripheral. 9.4.2.1 peripheral pin select function priority when a pin selectable peripheral is active on a given i/o pin, it takes priority over all other digital i/o and dig- ital communication peripherals associated with the pin. priority is given regardless of the type of peripheral that is mapped. pin select peripherals never take priority over any analog functions associated with the pin. 9.4.3 controlling peripheral pin select peripheral pin select features are controlled through two sets of special function registers: one to map peripheral inputs, and one to map outputs. because they are separately controlled, a particular peripheral?s input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. the association of a peripheral to a peripheral select- able pin is handled in two different ways, depending on if an input or an output is being mapped. 9.4.3.1 input mapping the inputs of the peripheral pin select options are mapped on the basis of the peripheral; that is, a control register associated with a peripheral dictates the pin it will be mapped to. the rpinrx registers are used to configure peripheral input mapping (see register 9-1 through register 9-14). each register contains two sets of 5-bit fields, with each set associated with one of the pin selectable peripherals. programming a given peripheral?s bit field with an appropriate 5-bit value maps the rpn pin with that value to that peripheral. for any given device, the valid range of values for any of the bit fields corresponds to the maximum number of peripheral pin selections supported by the device.
pic24fj64ga004 family ds39881b-page 100 preliminary ? 2007 microchip technology inc. table 9-1: selectable input sources (maps input to function) (1) 9.4.3.2 output mapping in contrast to inputs, the outputs of the peripheral pin select options are mapped on the basis of the pin. in this case, a control register associated with a particular pin dictates the peripheral output to be mapped. the rporx registers are used to control output mapping. like the rpinrx registers, each register contains two 5-bit fields; each field being associated with one rpn pin (see register 9-15). the value of the bit field corre- sponds to one of the peripherals and that peripheral?s output is mapped to the pin (see table 9-2). because of the mapping technique, the list of peripher- als for output mapping also includes a null value of ? 00000 ?. this permits any given pin to remain discon- nected from the output of any of the pin selectable peripherals. input name function name register configuration bits external interrupt 1 int1 rpinr0 intr1<4:0> external interrupt 2 int2 rpinr1 intr2r<4:0> timer2 external clock t2ck rpinr3 t2ckr<4:0> timer3 external clock t3ck rpinr3 t3ckr<4:0> timer4 external clock t4ck rpinr4 t4ckr<4:0> timer5 external clock t5ck rpinr4 t5ckr<4:0> input capture 1 ic1 rpinr7 ic1r<4:0> input capture 2 ic2 rpinr7 ic2r<4:0> input capture 3 ic3 rpinr8 ic3r<4:0> input capture 4 ic4 rpinr8 ic4r<4:0> input capture 5 ic5 rpinr9 ic5r<4:0> output compare fault a ocfa rpinr11 ocfar<4:0> output compare fault b ocfb rpinr11 ocfbr<4:0> uart1 receive u1rx rpinr18 u1rxr<4:0> uart1 clear to send u1cts rpinr18 u1ctsr<4:0> uart2 receive u2rx rpinr19 u2rxr<4:0> uart2 clear to send u2cts rpinr19 u2ctsr<4:0> spi1 data input sdi1 rpinr20 sdi1r<4:0> spi1 clock input sck1in rpinr20 sck1r<4:0> spi1 slave select input ss1in rpinr21 ss1r<4:0> spi2 data input sdi2 rpinr22 sdi2r<4:0> spi2 clock input sck2in rpinr22 sck2r<4:0> spi2 slave select input ss2in rpinr23 ss2r<4:0> note 1: unless otherwise noted, all inputs use the schmitt trigger input buffers.
? 2007 microchip technology inc. preliminary ds39881b-page 101 pic24fj64ga004 family table 9-2: selectable output sources (maps function to output) 9.4.3.3 mapping limitations the control schema of the peripheral pin select is extremely flexible. other than systematic blocks that prevent signal contention caused by two physical pins being configured as the same functional input or two functional outputs configured as the same pin, there are no hardware enforced lock outs. the flexibility extends to the point of allowing a single input to drive multiple peripherals or a single functional output to drive multiple output pins. 9.4.4 controlling configuration changes because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. pic24f devices include three features to prevent alterations to the peripheral map: ? control register lock sequence ? continuous state monitoring ? configuration bit remapping lock 9.4.4.1 control register lock under normal operation, writes to the rpinrx and rporx registers are not allowed; attempted writes will appear to execute normally, but the contents of the registers will remain unchanged. to change these reg- isters, they must be unlocked in hardware. the register lock is controlled by the iolock bit (osccon<6>). setting iolock prevents writes to the control registers; clearing iolock allows writes. to set or clear iolock, a specific command sequence must be executed: 1. write 46h to osccon<7:0>. 2. write 57h to osccon<7:0>. 3. clear (or set) iolock as a single operation. unlike the similar sequence with the oscillator?s lock bit, iolock remains in one state until changed. this allows all of the peripheral pin selects to be configured with a single unlock sequence followed by an update to all control registers, then locked with a second lock sequence. 9.4.4.2 continuous state monitoring in addition to being protected from direct writes, the contents of the rpinrx and rporx registers are constantly monitored in hardware by shadow registers. if an unexpected change in any of the registers occurs (such as cell disturbances caused by esd or other external events), a configuration mismatch reset will be triggered. 9.4.4.3 configuration bit pin select lock as an additional level of safety, the device can be con- figured to prevent more than one write session to the rpinrx and rporx registers. the iol1way (cw2<4>) configuration bit blocks the iolock bit from being cleared after it has been set once. if iolock remains set, the register unlock procedure will not execute and the peripheral pin select control regis- ters cannot be written to. the only way to clear the bit and re-enable peripheral remapping is to perform a device reset. in the default (unprogrammed) state, iol1way is set, restricting users to one write session. programming iol1way allows users unlimited access (with the proper use of the unlock sequence) to the peripheral pin select registers. function output function number (1) output name null (2) 0 null c1out 1 comparator 1 output c2out 2 comparator 2 output u1tx 3 uart1 transmit u1rts (3) 4 uart1 request to send u2tx 5 uart2 transmit u2rts (3) 6 uart2 request to send sdo1 7 spi1 data output sck1out 8 spi1 clock output ss1out 9 spi1 slave select output sdo2 10 spi2 data output sck2out 11 spi2 clock output ss2out 12 spi2 slave select output oc1 18 output compare 1 oc2 19 output compare 2 oc3 20 output compare 3 oc4 21 output compare 4 oc5 22 output compare 5 note 1: value assigned to the rpn<4:0> pins corre- sponds to the peripheral output function number. 2: the null function is assigned to all rpn outputs at device reset and disables the rpn output function. 3: irda ? bclk functionality uses this output.
pic24fj64ga004 family ds39881b-page 102 preliminary ? 2007 microchip technology inc. 9.4.5 considerations for peripheral pin selection the ability to control peripheral pin selection introduces several considerations into application design that could be overlooked. this is particularly true for several common peripherals that are available only as remappable peripherals. the main consideration is that the peripheral pin selects are not available on default pins in the device?s default (reset) state. since all rpinrx registers reset to ? 11111 ? and all rporx registers reset to ? 00000 ?, all peripheral pin select inputs are tied to rp31 and all peripheral pin select outputs are disconnected. this situation requires the user to initialize the device with the proper peripheral configuration before any other application code is executed. since the iolock bit resets in the unlocked state, it is not necessary to execute the unlock sequence after the device has come out of reset. for application safety, however, it is best to set iolock and lock the configuration after writing to the control registers. because the unlock sequence is timing critical, it must be executed as an assembly language routine, in the same manner as changes to the oscillator configura- tion. if the bulk of the application is written in c or another high-level language, the unlock sequence should be performed by writing inline assembly. choosing the configuration requires the review of all peripheral pin selects and their pin assignments, especially those that will not be used in the application. in all cases, unused pin-selectable peripherals should be disabled completely. unused peripherals should have their inputs assigned to an unused rpn pin function. i/o pins with unused rpn functions should be configured with the null peripheral output. the assignment of a peripheral to a particular pin does not automatically perform any other configuration of the pin?s i/o circuitry. in theory, this means adding a pin-selectable output to a pin may mean inadvertently driving an existing peripheral input when the output is driven. users must be familiar with the behavior of other fixed peripherals that share a remappable pin and know when to enable or disable them. to be safe, fixed digital peripherals that share the same pin should be disabled when not in use. along these lines, configuring a remappable pin for a specific peripheral does not automatically turn that fea- ture on. the peripheral must be specifically configured for operation and enabled, as if it were tied to a fixed pin. where this happens in the application code (immediately following device reset and peripheral configuration or inside the main application routine) depends on the peripheral and its use in the application. a final consideration is that peripheral pin select func- tions neither override analog inputs, nor reconfigure pins with analog functions for digital i/o. if a pin is configured as an analog input on device reset, it must be explicitly reconfigured as digital i/o when used with a peripheral pin select. example 9-2 shows a configuration for bidirectional communication with flow control using uart1. the following input and output functions are used: ? input functions: u1rx, u1cts ? output functions: u1tx, u1rts example 9-2: configuring uart1 input and output functions note: in tying peripheral pin select inputs to rp31, rp31 does not have to exist on a device for the registers to be reset to it. //************************************* // unlock registers //************************************* asm volatile ( "mov #osccon, w1 \n" "mov #0x46, w2 \n" "mov #0x57, w3 \n" "mov.b w2, \n" "mov.b w3, \n" "bclr osccon,#6"); //*************************** // configure input functions // (see table 9-1) //*************************** //*************************** // assign u1rx to pin rp0 //*************************** rpinr18bits.u1rxr = 0; //*************************** // assign u1cts to pin rp1 //*************************** rpinr18bits.u1ctsr = 1; //*************************** // configure output functions // (see table 9-2) //*************************** //*************************** // assign u1tx to pin rp2 //*************************** rpor1bits.rp2r = 3; //*************************** // assign u1rts to pin rp3 //*************************** rpor1bits.rp3r = 4; //************************************* // lock registers //************************************* asm volatile ( "mov #osccon, w1 \n" "mov #0x46, w2 \n" "mov #0x57, w3 \n" "mov.b w2, \n" "mov.b w3, \n" "bset osccon, #6" );
? 2007 microchip technology inc. preliminary ds39881b-page 103 pic24fj64ga004 family 9.5 peripheral pin select registers the pic24fj64ga004 family of devices implements a total of 27 registers for remappable peripheral configuration: ? input remappable peripheral registers (14) ? output remappable peripheral registers (13) note: input and output register values can only be changed if osccon = 0 . see section 9.4.4.1 ?control register lock? for a specific command sequence. register 9-1: rpinr0: peripheral pin select input register 0 u-0 u-0 u-0 r/w -1 r/w -1 r/w -1 r/w -1 r/w -1 ? ? ? intr1r4 intr1r3 intr1r2 intr1r1 intr1r0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 intr1r4:intr1r0: assign external interrupt 1 (int1) to the corresponding rpn pin bits bit 7-0 unimplemented: read as ? 0 ? register 9-2: rpinr1: peripheral pin select input register 1 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 r/w -1 r/w -1 r/w -1 r/w -1 r/w -1 ? ? ? intr2r4 intr2r3 intr2r2 intr2r1 intr2r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-5 unimplemented: read as ? 0 ? bit 4-0 intr2r4:intr2r0: assign external interrupt 2 (int2) to the corresponding rpn pin bits
pic24fj64ga004 family ds39881b-page 104 preliminary ? 2007 microchip technology inc. register 9-3: rpinr3: peripheral pin select input register 3 u-0 u-0 u-0 r/w -1 r/w -1 r/w -1 r/w -1 r/w -1 ? ? ? t3ckr4 t3ckr3 t3ckr2 t3ckr1 t3ckr0 bit 15 bit 8 u-0 u-0 u-0 r/w -1 r/w -1 r/w -1 r/w -1 r/w -1 ? ? ? t2ckr4 t2ckr3 t2ckr2 t2ckr1 t2ckr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 t3ckr4:t3ckr0: assign timer3 external clock (t3ck) to the corresponding rpn pin bits bit 7-5 unimplemented: read as ? 0 ? bit 4-0 t2ckr4:t2ckr0: assign timer2 external clock (t2ck) to the corresponding rpn pin bits register 9-4: rpinr4: peripheral pin select input register 4 u-0 u-0 u-0 r/w -1 r/w -1 r/w -1 r/w -1 r/w -1 ? ? ? t5ckr4 t5ckr3 t5ckr2 t5ckr1 t5ckr0 bit 15 bit 8 u-0 u-0 u-0 r/w -1 r/w -1 r/w -1 r/w -1 r/w -1 ? ? ? t4ckr4 t4ckr3 t4ckr2 t4ckr1 t4ckr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 t5ckr4:t5ckr0: assign timer5 external clock (t5ck) to the corresponding rpn pin bits bit 7-5 unimplemented: read as ? 0 ? bit 4-0 t4ckr4:t4ckr0: assign timer4 external clock (t4ck) to the corresponding rpn pin bits
? 2007 microchip technology inc. preliminary ds39881b-page 105 pic24fj64ga004 family register 9-5: rpinr7: peripheral pin select input register 7 u-0 u-0 u-0 r/w -1 r/w -1 r/w -1 r/w -1 r/w -1 ? ? ? ic2r4 ic2r3 ic2r2 ic2r1 ic2r0 bit 15 bit 8 u-0 u-0 u-0 r/w -1 r/w -1 r/w -1 r/w -1 r/w -1 ? ? ? ic1r4 ic1r3 ic1r2 ic1r1 ic1r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 ic2r4:ic2r0: assign input capture 2 (ic2) to the corresponding rpn pin bits bit 7-5 unimplemented: read as ? 0 ? bit 4-0 ic1r4:ic1r0: assign input capture 1 (ic1) to the corresponding rpn pin bits register 9-6: rpinr8: peripheral pin select input register 8 u-0 u-0 u-0 r/w -1 r/w -1 r/w -1 r/w -1 r/w -1 ? ? ? ic4r4 ic4r3 ic4r2 ic4r1 ic4r0 bit 15 bit 8 u-0 u-0 u-0 r/w -1 r/w -1 r/w -1 r/w -1 r/w -1 ? ? ? ic3r4 ic3r3 ic3r2 ic3r1 ic3r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 ic4r4:ic4r0: assign input capture 4 (ic4) to the corresponding rpn pin bits bit 7-5 unimplemented: read as ? 0 ? bit 4-0 ic3r4:ic3r0: assign input capture 3 (ic3) to the corresponding rpn pin bits
pic24fj64ga004 family ds39881b-page 106 preliminary ? 2007 microchip technology inc. register 9-7: rpinr9: peripheral pin select input register 9 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 r/w -1 r/w -1 r/w -1 r/w -1 r/w -1 ? ? ? ic5r4 ic5r3 ic5r2 ic5r1 ic5r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-5 unimplemented: read as ? 0 ? bit 4-0 ic5r4:ic5r0: assign input capture 5 (ic5) to the corresponding rpn pin bits register 9-8: rpinr11: peripheral pin select input register 11 u-0 u-0 u-0 r/w -1 r/w -1 r/w -1 r/w -1 r/w -1 ? ? ? ocfbr4 ocfbr3 ocfbr2 ocfbr1 ocfbr0 bit 15 bit 8 u-0 u-0 u-0 r/w -1 r/w -1 r/w -1 r/w -1 r/w -1 ? ? ? ocfar4 ocfar3 ocfar2 ocfar1 ocfar0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 ocfbr4:ocfbr0: assign output compare fault a (ocfa) to the corresponding rpn pin bits bit 7-5 unimplemented: read as ? 0 ? bit 4-0 ocfar4:ocfar0: assign output compare fault b (ocfb) to the corresponding rpn pin bits
? 2007 microchip technology inc. preliminary ds39881b-page 107 pic24fj64ga004 family register 9-9: rpinr18: peripheral pin select input register 18 u-0 u-0 u-0 r/w -1 r/w -1 r/w -1 r/w -1 r/w -1 ? ? ? u1ctsr4 u1ctsr3 u1ctsr2 u1ctsr1 u1ctsr0 bit 15 bit 8 u-0 u-0 u-0 r/w -1 r/w -1 r/w -1 r/w -1 r/w -1 ? ? ? u1rxr4 u1rxr3 u1rxr2 u1rxr1 u1rxr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 u1ctsr4:u1ctsr0: assign uart1 clear to send (u1cts) to the corresponding rpn pin bits bit 7-5 unimplemented: read as ? 0 ? bit 4-0 u1rxr4:u1rxr0: assign uart1 receive (u1rx) to the corresponding rpn pin bits register 9-10: rpinr19: peripheral pin select input register 19 u-0 u-0 u-0 r/w -1 r/w -1 r/w -1 r/w -1 r/w -1 ? ? ? u2ctsr4 u2ctsr3 u2ctsr2 u2ctsr1 u2ctsr0 bit 15 bit 8 u-0 u-0 u-0 r/w -1 r/w -1 r/w -1 r/w -1 r/w -1 ? ? ? u2rxr4 u2rxr3 u2rxr2 u2rxr1 u2rxr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 u2ctsr4:u2ctsr0: assign uart2 clear to send (u2cts) to the corresponding rpn pin bits bit 7-5 unimplemented: read as ? 0 ? bit 4-0 u2rxr4:u2rxr0: assign uart2 receive (u2rx) to the corresponding rpn pin bits
pic24fj64ga004 family ds39881b-page 108 preliminary ? 2007 microchip technology inc. register 9-11: rpinr20: peripheral pin select input register 20 u-0 u-0 u-0 r/w -1 r/w -1 r/w -1 r/w -1 r/w -1 ? ? ? sck1r4 sck1r3 sck1r2 sck1r1 sck1r0 bit 15 bit 8 u-0 u-0 u-0 r/w -1 r/w -1 r/w -1 r/w -1 r/w -1 ? ? ? sdi1r4 sdi1r3 sdi1r2 sdi1r1 sdi1r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 sck1r4:sck1r0: assign spi1 clock input (sck1in) to the corresponding rpn pin bits bit 7-5 unimplemented: read as ? 0 ? bit 4-0 sdi1r4:sdi1r0: assign spi1 data input (sdi1) to the corresponding rpn pin bits register 9-12: rpinr21: peripheral pin select input register 21 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 r/w -1 r/w -1 r/w -1 r/w -1 r/w -1 ? ? ? ss1r4 ss1r3 ss1r2 ss1r1 ss1r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-5 unimplemented: read as ? 0 ? bit 4-0 ss1r4:ss1r0: assign spi1 slave select input (ss1in) to the corresponding rpn pin bits
? 2007 microchip technology inc. preliminary ds39881b-page 109 pic24fj64ga004 family register 9-13: rpinr22: peripheral pin select input register 22 u-0 u-0 u-0 r/w -1 r/w -1 r/w -1 r/w -1 r/w -1 ? ? ? sck2r4 sck2r3 sck2r2 sck2r1 sck2r0 bit 15 bit 8 u-0 u-0 u-0 r/w -1 r/w -1 r/w -1 r/w -1 r/w -1 ? ? ? sdi2r4 sdi2r3 sdi2r2 sdi2r1 sdi2r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 sck2r4:sck2r0: assign spi2 clock input (sck2in) to the corresponding rpn pin bits bit 7-5 unimplemented: read as ? 0 ? bit 4-0 sdi2r4:sdi2r0: assign spi2 data input (sdi2) to the corresponding rpn pin bits register 9-14: rpinr23: peripheral pin select input register 23 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 r/w -1 r/w -1 r/w -1 r/w -1 r/w -1 ? ? ? ss2r4 ss2r3 ss2r2 ss2r1 ss2r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-5 unimplemented: read as ? 0 ? bit 4-0 ss2r4:ss2r0: assign spi2 slave select input (ss2in) to the corresponding rpn pin bits
pic24fj64ga004 family ds39881b-page 110 preliminary ? 2007 microchip technology inc. register 9-15: rpor0: peripheral pin select output register 0 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ? rp1r4 rp1r3 rp1r2 rp1r1 rp1r0 bit 15 bit 8 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ? rp0r4 rp0r3 rp0r2 rp0r1 rp0r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp1r4:rp1r0: peripheral output function is assigned to rp1 output pin bits (see table 9-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp0r4:rp0r0: peripheral output function is assigned to rp0 output pin bits (see table 9-2 for peripheral function numbers) register 9-16: rpor1: peripheral pin select output register 1 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ? rp3r4 rp3r3 rp3r2 rp3r1 rp3r0 bit 15 bit 8 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ? rp2r4 rp2r3 rp2r2 rp2r1 rp2r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp3r4:rp3r0: peripheral output function is assigned to rp3 output pin bits (see table 9-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp2r4:rp2r0: peripheral output function is assigned to rp2 output pin bits (see table 9-2 for peripheral function numbers)
? 2007 microchip technology inc. preliminary ds39881b-page 111 pic24fj64ga004 family register 9-17: rpor2: peripheral pin select output register 2 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ? rp5r4 rp5r3 rp5r2 rp5r1 rp5r0 bit 15 bit 8 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ? rp4r4 rp4r3 rp4r2 rp4r1 rp4r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp5r4:rp5r0: peripheral output function is assigned to rp5 output pin bits (see table 9-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp4r4:rp4r0: peripheral output function is assigned to rp4 output pin bits (see table 9-2 for peripheral function numbers) register 9-18: rpor3: peripheral pin select output register 3 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ? rp7r4 rp7r3 rp7r2 rp7r1 rp7r0 bit 15 bit 8 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ? rp6r4 rp6r3 rp6r2 rp6r1 rp6r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp7r4:rp7r0: peripheral output function is assigned to rp7 output pin bits (see table 9-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp6r4:rp6r0: peripheral output function is assigned to rp6 output pin bits (see table 9-2 for peripheral function numbers)
pic24fj64ga004 family ds39881b-page 112 preliminary ? 2007 microchip technology inc. register 9-19: rpor4: peripheral pin select output register 4 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ? rp9r4 rp9r3 rp9r2 rp9r1 rp9r0 bit 15 bit 8 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ? rp8r4 rp8r3 rp8r2 rp8r1 rp8r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp9r4:rp9r0: peripheral output function is assigned to rp9 output pin bits (see table 9-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp8r4:rp8r0: peripheral output function is assigned to rp8 output pin bits (see table 9-2 for peripheral function numbers) register 9-20: rpor5: peripheral pin select output register 5 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ? rp11r4 rp11r3 rp11r2 rp11r1 rp11r0 bit 15 bit 8 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ? rp10r4 rp10r3 rp10r2 rp10r1 rp10r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp11r4:rp11r0: peripheral output function is assigned to rp11 output pin bits (see table 9-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp10r4:rp10r0: peripheral output function is assigned to rp10 output pin bits (see table 9-2 for peripheral function numbers)
? 2007 microchip technology inc. preliminary ds39881b-page 113 pic24fj64ga004 family register 9-21: rpor6: peripheral pin select output register 6 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ? rp13r4 rp13r3 rp13r2 rp13r1 rp13r0 bit 15 bit 8 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ? rp12r4 rp12r3 rp12r2 rp12r1 rp12r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp13r4:rp13r0: peripheral output function is assigned to rp13 output pin bits (see table 9-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp12r4:rp12r0: peripheral output function is assigned to rp12 output pin bits (see table 9-2 for peripheral function numbers) register 9-22: rpor7: peripheral pin select output register 7 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ? rp15r4 rp15r3 rp15r2 rp15r1 rp15r0 bit 15 bit 8 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ? rp14r4 rp14r3 rp14r2 rp14r1 rp14r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp15r4:rp15r0: peripheral output function is assigned to rp15 output pin bits (see table 9-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp14r4:rp14r0: peripheral output function is assigned to rp14 output pin bits (see table 9-2 for peripheral function numbers)
pic24fj64ga004 family ds39881b-page 114 preliminary ? 2007 microchip technology inc. register 9-23: rpor8: peripheral pin select output register 8 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ? rp17r4 rp17r3 rp17r2 rp17r1 rp17r0 bit 15 bit 8 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ? rp16r4 rp16r3 rp16r2 rp16r1 rp16r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp17r4:rp17r0: peripheral output function is assigned to rp17 output pin bits (see table 9-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp16r4:rp16r0: peripheral output function is assigned to rp16 output pin bits (see table 9-2 for peripheral function numbers) register 9-24: rpor9: peripheral pin select output register 9 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ? rp19r4 rp19r3 rp19r2 rp19r1 rp19r0 bit 15 bit 8 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ? rp18r4 rp18r3 rp18r2 rp18r1 rp18r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp19r4:rp19r0: peripheral output function is assigned to rp19 output pin bits (see table 9-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp18r4:rp18r0: peripheral output function is assigned to rp18 output pin bits (see table 9-2 for peripheral function numbers)
? 2007 microchip technology inc. preliminary ds39881b-page 115 pic24fj64ga004 family register 9-25: rpor10: peripheral pin select output register 10 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ? rp21r4 rp21r3 rp21r2 rp21r1 rp21r0 bit 15 bit 8 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ? rp20r4 rp20r3 rp20r2 rp20r1 rp20r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp21r4:rp21r0: peripheral output function is assigned to rp21 output pin bits (see table 9-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp20r4:rp20r0: peripheral output function is assigned to rp20 output pin bits (see table 9-2 for peripheral function numbers) register 9-26: rpor11: peripheral pin select output register 11 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ? rp23r4 rp23r3 rp23r2 rp23r1 rp23r0 bit 15 bit 8 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ? rp22r4 rp22r3 rp22r2 rp22r1 rp22r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp23r4:rp23r0: peripheral output function is assigned to rp23 output pin bits (see table 9-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp22r4:rp22r0: peripheral output function is assigned to rp22 output pin bits (see table 9-2 for peripheral function numbers)
pic24fj64ga004 family ds39881b-page 116 preliminary ? 2007 microchip technology inc. register 9-27: rpor12: peripheral pin select output register 12 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ? rp25r4 rp25r3 rp25r2 rp25r1 rp25r0 bit 15 bit 8 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ? rp24r4 rp24r3 rp24r2 rp24r1 rp24r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp25r4:rp25r0: peripheral output function is assigned to rp25 output pin bits (see table 9-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp24r4:rp24r0: peripheral output function is assigned to rp24 output pin bits (see table 9-2 for peripheral function numbers)
? 2007 microchip technology inc. preliminary ds39881b-page 117 pic24fj64ga004 family 10.0 timer1 the timer1 module is a 16-bit timer which can serve as the time counter for the real-time clock (rtc), or operate as a free-running interval timer/counter. timer1 can operate in three modes: ?16-bit timer ? 16-bit synchronous counter ? 16-bit asynchronous counter timer1 also supports these features: ? timer gate operation ? selectable prescaler settings ? timer operation during cpu idle and sleep modes ? interrupt on 16-bit period register match or falling edge of external gate signal figure 10-1 presents a block diagram of the 16-bit timer module. to configure timer1 for operation: 1. set the ton bit (= 1 ). 2. select the timer prescaler ratio using the tckps1:tckps0 bits. 3. set the clock and gating modes using the tcs and tgate bits. 4. set or clear the tsync bit to configure synchronous or asynchronous operation. 5. load the timer period value into the pr1 register. 6. if interrupts are required, set the interrupt enable bit, t1ie. use the priority bits, t1ip2:t1ip0, to set the interrupt priority. figure 10-1: 16-bit timer1 module block diagram note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the associated ?pic24f family reference manual? chapter. ton sync sosci sosco/ pr1 set t1if equal comparator tmr1 reset soscen 1 0 tsync q qd ck tckps1:tckps0 prescaler 1, 8, 64, 256 2 tgate t cy 1 0 t1ck tcs 1x 01 tgate 00 gate sync
pic24fj64ga004 family ds39881b-page 118 preliminary ? 2007 microchip technology inc. register 10-1: t1con: ti mer1 control register r/w -0 u-0 r/w -0 u-0 u-0 u-0 u-0 u-0 ton ?tsidl ? ? ? ? ? bit 15 bit 8 u-0 r/w -0 r/w -0 r/w -0 u-0 r/w -0 r/w -0 u-0 ? tgate tckps1 tckps0 ? tsync tcs ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ton: timer1 on bit 1 = starts 16-bit timer1 0 = stops 16-bit timer1 bit 14 unimplemented: read as ? 0 ? bit 13 tsidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-7 unimplemented: read as ? 0 ? bit 6 tgate: timer1 gated time accumulation enable bit when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = gated time accumulation enabled 0 = gated time accumulation disabled bit 5-4 tckps1:tckps0: timer1 input clock prescale select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 unimplemented: read as ? 0 ? bit 2 tsync: timer1 external clock input synchronization select bit when tcs = 1 : 1 = synchronize external clock input 0 = do not synchronize external clock input when tcs = 0 : this bit is ignored. bit 1 tcs: timer1 clock source select bit 1 = external clock from t1ck pin (on the rising edge) 0 = internal clock (f osc /2) bit 0 unimplemented: read as ? 0 ?
? 2007 microchip technology inc. preliminary ds39881b-page 119 pic24fj64ga004 family 11.0 timer2/3 and timer4/5 the timer2/3 and timer4/5 modules are 32-bit timers, which can also be configured as four independent 16-bit timers with selectable operating modes. as a 32-bit timer, timer2/3 and timer4/5 operate in three modes: ? two independent 16-bit timers (timer2 and timer3) with all 16-bit operating modes (except asynchronous counter mode) ? single 32-bit timer ? single 32-bit synchronous counter they also support these features: ? timer gate operation ? selectable prescaler settings ? timer operation during idle and sleep modes ? interrupt on a 32-bit period register match ? adc event trigger (timer4/5 only) individually, all four of the 16-bit timers can function as synchronous timers or counters. they also offer the features listed above, except for the adc event trigger; this is implemented only with timer5. the operating modes and enabled features are determined by setting the appropriate bit(s) in the t2con, t3con, t4con and t5con registers. t2con and t4con are shown in generic form in register 11-1; t3con and t5con are shown in register 11-2. for 32-bit timer/counter operation, timer2 and timer4 are the least significant word; timer3 and timer4 are the most significant word of the 32-bit timers. to configure timer2/3 or timer4/5 for 32-bit operation: 1. set the t32 bit (t2con<3> or t4con<3> = 1 ). 2. select the prescaler ratio for timer2 or timer4 using the tckps1:tckps0 bits. 3. set the clock and gating modes using the tcs and tgate bits. if tcs is set to external clock, rpinrx (txck) must be configured to an avail- able rpn pin. see section 9.4 ?peripheral pin select? for more information. 4. load the timer period value. pr3 (or pr5) will contain the most significant word of the value while pr2 (or pr4) contains the least significant word. 5. if interrupts are required, set the interrupt enable bit, t3ie or t5ie; use the priority bits, t3ip2:t3ip0 or t5ip2:t5ip0, to set the interrupt priority. note that while timer2 or timer4 con- trols the timer, the interrupt appears as a timer3 or timer5 interrupt. 6. set the ton bit (= 1 ). the timer value at any point is stored in the register pair, tmr3:tmr2 (or tmr5:tmr4). tmr3 (tmr5) always contains the most significant word of the count, while tmr2 (tmr4) contains the least significant word. to configure any of the timers for individual 16-bit operation: 1. clear the t32 bit corresponding to that timer (t2con<3> for timer2 and timer3 or t4con<3> for timer4 and timer5). 2. select the timer prescaler ratio using the tckps1:tckps0 bits. 3. set the clock and gating modes using the tcs and tgate bits. see section 9.4 ?peripheral pin select? for more information. 4. load the timer period value into the prx register. 5. if interrupts are required, set the interrupt enable bit, txie; use the priority bits, txip2:txip0, to set the interrupt priority. 6. set the ton bit (txcon<15> = 1 ). note 1: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the associated ?pic24f family reference manual? chapter. 2: this peripheral contains input functions that may need to be configured by the peripheral pin select feature. for more information, see section 9.4 ?peripheral pin select? . note: for 32-bit operation, t3con and t5con control bits are ignored. only t2con and t4con control bits are used for setup and control. timer2 and timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the timer3 or timer5 interrupt flags.
pic24fj64ga004 family ds39881b-page 120 preliminary ? 2007 microchip technology inc. figure 11-1: timer2/3 and timer4/5 (32-bit) block diagram tmr3 tmr2 set t3if (t5if) equal comparator pr3 pr2 reset lsb msb note 1: the 32-bit timer configuration bit, t32, must be set for 32-bit timer/counter operation. all control bits are respective to the t2con and t4con registers. 2: this peripheral?s inputs must be assigned to an available rpn pin before use. please see section 9.4 ?peripheral pin select? for more information. 3: the adc event trigger is available only on timer4/5. data bus<15:0> tmr3h read tmr2 (tmr4) (1) write tmr2 (tmr4) (1) 16 16 16 q qd ck tgate 0 1 ton tckps1:tckps0 prescaler 1, 8, 64, 256 2 t cy tcs (2) tgate (2) gate t2ck sync adc event trigger (3) sync (t4ck) (pr5) (pr4) (tmr5h) (tmr5) (tmr4) 1x 01 00
? 2007 microchip technology inc. preliminary ds39881b-page 121 pic24fj64ga004 family figure 11-2: timer2 and timer4 (16-bit synchronous) block diagram figure 11-3: timer3 and timer5 (16-bit asynchronous) block diagram ton tckps1:tckps0 prescaler 1, 8, 64, 256 2 t cy tcs (1) 1x 01 tgate (1) 00 gate t2ck sync pr2 (pr4) set t2if (t4if) equal comparator tmr2 (tmr4) reset q qd ck tgate 1 0 (t4ck) sync note 1: this peripheral?s inputs must be assigned to an available rpn pin before use. please see section 9.4 ?peripheral pin select? for more information. ton tckps1:tckps0 2 t cy tcs (1) 1x 01 tgate (1) 00 t3ck pr3 (pr5) set t3if (t5if) equal comparator tmr3 (tmr5) reset q q d ck tgate 1 0 adc event trigger (2) (t5ck) prescaler 1, 8, 64, 256 sync note 1: this peripheral?s inputs must be assigned to an available rpn pin before use. please see section 9.4 ?peripheral pin select? for more information. 2: the adc event trigger is available only on timer4/5.
pic24fj64ga004 family ds39881b-page 122 preliminary ? 2007 microchip technology inc. register 11-1: txcon: timer2 and timer4 control register r/w -0 u-0 r/w -0 u-0 u-0 u-0 u-0 u-0 ton ?tsidl ? ? ? ? ? bit 15 bit 8 u-0 r/w -0 r/w -0 r/w -0 r/w -0 u-0 r/w -0 u-0 ? tgate tckps1 tckps0 t32 (1) ?tcs (2) ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ton: timerx on bit when txcon<3> = 1 : 1 = starts 32-bit timerx/y 0 = stops 32-bit timerx/y when txcon<3> = 0 : 1 = starts 16-bit timerx 0 = stops 16-bit timerx bit 14 unimplemented: read as ? 0 ? bit 13 tsidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-7 unimplemented: read as ? 0 ? bit 6 tgate: timerx gated time accumulation enable bit when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = gated time accumulation enabled 0 = gated time accumulation disabled bit 5-4 tckps1:tckps0: timerx input clock prescale select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 t32: 32-bit timer mode select bit (1) 1 = timerx and timery form a single 32-bit timer 0 = timerx and timery act as two 16-bit timers in 32-bit mode, t3con control bits do not affect 32-bit timer operation. bit 2 unimplemented: read as ? 0 ? bit 1 tcs: timerx clock source select bit (2) 1 = external clock from pin, txck (on the rising edge) 0 = internal clock (f osc /2) bit 0 unimplemented: read as ? 0 ? note 1: in 32-bit mode, the t3con or t5con control bits do not affect 32-bit timer operation. 2: if tcs = 1 , rpinrx (txck) must be configured to an available rpn pin. for more information, see section 9.4 ?peripheral pin select? .
? 2007 microchip technology inc. preliminary ds39881b-page 123 pic24fj64ga004 family register 11-2: tycon: timer3 and timer5 control register r/w -0 u-0 r/w -0 u-0 u-0 u-0 u-0 u-0 ton (1) ?tsidl (1) ? ? ? ? ? bit 15 bit 8 u-0 r/w -0 r/w -0 r/w -0 u-0 u-0 r/w -0 u-0 ?tgate (1) tckps1 (1) tckps0 (1) ? ?tcs (1,2) ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ton: timery on bit (1) 1 = starts 16-bit timery 0 = stops 16-bit timery bit 14 unimplemented: read as ? 0 ? bit 13 tsidl: stop in idle mode bit (1) 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-7 unimplemented: read as ? 0 ? bit 6 tgate: timery gated time accumulation enable bit (1) when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = gated time accumulation enabled 0 = gated time accumulation disabled bit 5-4 tckps1:tckps0: timery input clock prescale select bits (1) 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3-2 unimplemented: read as ? 0 ? bit 1 tcs: timery clock source select bit (1,2) 1 = external clock from pin tyck (on the rising edge) 0 = internal clock (f osc /2) bit 0 unimplemented: read as ? 0 ? note 1: when 32-bit operation is enabled (t2con<3> or t4con<3> = 1 ), these bits have no effect on timery operation; all timer functions are set through t2con and t4con. 2: if tcs = 1 , rpinrx (txck) must be configured to an available rpn pin. see section 9.4 ?peripheral pin select? for more information.
pic24fj64ga004 family ds39881b-page 124 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds39881b-page 125 pic24fj64ga004 family 12.0 input capture figure 12-1: input capture block diagram note 1: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the associated ?pic24f family reference manual? chapter. 2: this peripheral contains input functions that may need to be configured by the peripheral pin select feature. for more information, see section 9.4 ?peripheral pin select? . icxbuf icx pin icm<2:0> (icxcon<2:0>) mode select 3 10 set flag icxif (in ifsn register) tmry tmrx edge detection logic 16 16 fifo r/w logic ici<1:0> icov, icbne (icxcon<4:3>) icxcon interrupt logic system bus from 16-bit timers ictmr (icxcon<7>) fifo prescaler counter (1, 4, 16) and clock synchronizer note 1: an ?x? in a signal, register or bit nam e denotes the number of the capture channel. 2: this peripheral?s inputs must be assigned to an available rpn pin before use. please see section 9.4 ?peripheral pin select? for more information.
pic24fj64ga004 family ds39881b-page 126 preliminary ? 2007 microchip technology inc. 12.1 input capture registers register 12-1: icxcon: input capture x control register u-0 u-0 r/w -0 u-0 u-0 u-0 u-0 u-0 ? ?icsidl ? ? ? ? ? bit 15 bit 8 r/w -0 r/w -0 r/w -0 r-0, hc r-0, hc r/w -0 r/w -0 r/w -0 ictmr ici1 ici0 icov icbne icm2 icm1 icm0 bit 7 bit 0 legend: hc = hardware clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 icsidl: input capture x module stop in idle control bit 1 = input capture module will halt in cpu idle mode 0 = input capture module will continue to operate in cpu idle mode bit 12-8 unimplemented: read as ? 0 ? bit 7 ictmr: input capture x timer select bit 1 = tmr2 contents are captured on capture event 0 = tmr3 contents are captured on capture event bit 6-5 ici1:ici0: select number of captures per interrupt bits 11 = interrupt on every fourth capture event 10 = interrupt on every third capture event 01 = interrupt on every second capture event 00 = interrupt on every capture event bit 4 icov: input capture x overflow status flag (read-only) bit 1 = input capture overflow occurred 0 = no input capture overflow occurred bit 3 icbne: input capture x buffer empty status (read-only) bit 1 = input capture buffer is not empty, at least one more capture value can be read 0 = input capture buffer is empty bit 2-0 icm2:icm0: input capture x mode select bits (1) 111 = input capture functions as interrupt pin only when device is in sleep or idle mode (rising edge detect only, all other control bits are not applicable) 110 = unused (module disabled) 101 = capture mode, every 16th rising edge 100 = capture mode, every 4th rising edge 011 = capture mode, every rising edge 010 = capture mode, every falling edge 001 = capture mode, every edge (rising and falling) ? ici<1:0> bits do not control interrupt generation for this mode 000 = input capture module turned off note 1: rpinrx (icxrx) must be configured to an available rpn pin. for more information, see section 9.4 ?peripheral pin select? .
? 2007 microchip technology inc. preliminary ds39881b-page 127 pic24fj64ga004 family 13.0 output compare 13.1 setup for single output pulse generation when the ocm control bits (ocxcon<2:0>) are set to ? 100 ?, the selected output compare channel initializes the ocx pin to the low state and generates a single output pulse. to generate a single output pulse, the following steps are required (these steps assume the timer source is initially turned off, but this is not a requirement for the module operation): 1. determine the instruction clock cycle time. take into account the frequency of the external clock to the timer source (if one is used) and the timer prescaler settings. 2. calculate time to the rising edge of the output pulse relative to the tmry start value (0000h). 3. calculate the time to the falling edge of the pulse based on the desired pulse width and the time to the rising edge of the pulse. 4. write the values computed in steps 2 and 3 above into the output compare x register, ocxr, and the output compare x secondary register, ocxrs, respectively. 5. set timer period register, pry, to value equal to or greater than value in ocxrs, the output compare x secondary register. 6. set the ocm bits to ? 100 ? and the octsel (ocxcon<3>) bit to the desired timer source. the ocx pin state will now be driven low. 7. set the ton (tycon<15>) bit to ? 1 ?, which enables the compare time base to count. 8. upon the first match between tmry and ocxr, the ocx pin will be driven high. 9. when the incrementing timer, tmry, matches the output compare x secondary register, ocxrs, the second and trailing edge (high-to-low) of the pulse is driven onto the ocx pin. no additional pulses are driven onto the ocx pin and it remains at low. as a result of the second compare match event, the ocxif interrupt flag bit is set, which will result in an interrupt if it is enabled, by set- ting the ocxie bit. for further information on peripheral interrupts, refer to section 6.0 ?interrupt controller? . 10. to initiate another single pulse output, change the timer and compare register settings, if needed, and then issue a write to set the ocm bits to ? 100 ?. disabling and re-enabling of the timer and clear- ing the tmry register are not required, but may be advantageous for defining a pulse from a known event time boundary. the output compare module does not have to be dis- abled after the falling edge of the output pulse. another pulse can be initiated by rewriting the value of the ocxcon register. 13.2 setup for continuous output pulse generation when the ocm control bits (ocxcon<2:0>) are set to ? 101 ?, the selected output compare channel initializes the ocx pin to the low state and generates output pulses on each and every compare match event. for the user to configure the module for the generation of a continuous stream of output pulses, the following steps are required (these steps assume the timer source is initially turned off, but this is not a requirement for the module operation): 1. determine the instruction clock cycle time. take into account the frequency of the external clock to the timer source (if one is used) and the timer prescaler settings. 2. calculate time to the rising edge of the output pulse relative to the tmry start value (0000h). 3. calculate the time to the falling edge of the pulse based on the desired pulse width and the time to the rising edge of the pulse. 4. write the values computed in step 2 and 3 above into the output compare x register, ocxr, and the output compare x secondary register, ocxrs, respectively. 5. set timer period register, pry, to value equal to or greater than value in ocxrs. 6. set the ocm bits to ? 101 ? and the octsel bit to the desired timer source. the ocx pin state will now be driven low. 7. enable the compare time base by setting the ton (tycon<15>) bit to ? 1 ?. 8. upon the first match between tmry and ocxr, the ocx pin will be driven high. 9. when the compare time base, tmry, matches the ocxrs, the second and trailing edge (high-to-low) of the pulse is driven onto the ocx pin. 10. as a result of the second compare match event, the ocxif interrupt flag bit set. 11. when the compare time base and the value in its respective timer period register match, the tmry register resets to 0x0000 and resumes counting. 12. steps 8 through 11 are repeated and a continuous stream of pulses is generated indefinitely. the ocxif flag is set on each ocxrs/tmry compare match event. note 1: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the associated ?pic24f family reference manual? chapter. 2: this peripheral contains input functions that may need to be configured by the peripheral pin select feature. for more information, see section 9.4 ?peripheral pin select? .
pic24fj64ga004 family ds39881b-page 128 preliminary ? 2007 microchip technology inc. 13.3 pulse-width modulation mode the following steps should be taken when configuring the output compare module for pwm operation: 1. set the pwm period by writing to the selected timer period register (pry). 2. set the pwm duty cycle by writing to the ocxrs register. 3. write the ocxr register with the initial duty cycle. 4. enable interrupts, if required, for the timer and output compare modules. the output compare interrupt is required for pwm fault pin utilization. 5. configure the output compare module for one of two pwm operation modes by writing to the output compare mode bits, ocm<2:0> (ocxcon<2:0>). 6. set the tmry prescale value and enable the time base by setting ton (txcon<15>) = 1 . 13.3.1 pwm period the pwm period is specified by writing to pry, the timer period register. the pwm period can be calculated using equation 13-1. equation 13-1: calculating the pwm period (1) 13.3.2 pwm duty cycle the pwm duty cycle is specified by writing to the ocxrs register. the ocxrs register can be written to at any time, but the duty cycle value is not latched into ocxr until a match between pry and tmry occurs (i.e., the period is complete). this provides a double buffer for the pwm duty cycle and is essential for glitch- less pwm operation. in the pwm mode, ocxr is a read-only register. some important boundary parameters of the pwm duty cycle include: ? if the output compare x register, ocxr, is loaded with 0000h, the ocx pin will remain low (0% duty cycle). ? if ocxr is greater than pry (timer period register), the pin will remain high (100% duty cycle). ? if ocxr is equal to pry, the ocx pin will be low for one time base count value and high for all other count values. see example 13-1 for pwm mode timing details. table 13-1 shows example pwm frequencies and resolutions for a device operating at 10 mips. equation 13-2: calculation for maximum pwm resolution (1) note: this peripheral contains input and output functions that may need to be configured by the peripheral pin select. see section 9.4 ?peripheral pin select? for more information. note: the ocxr register should be initialized before the output compare module is first enabled. the ocxr register becomes a read-only duty cycle register when the module is operated in the pwm modes. the value held in ocxr will become the pwm duty cycle for the first pwm period. the contents of the output compare x secondary register, ocxrs, will not be transferred into ocxr until a time base period match occurs. note: a pry value of n will produce a pwm period of n + 1 time base count cycles. for example, a value of 7 written into the pry register will yield a period consisting of 8 time base cycles. pwm period = [(pry) + 1] ? t cy ? (timer prescale value) pwm frequency = 1/[pwm period] where: note 1: based on t cy = t cy /2; doze mode and pll are disabled. ( ) maximum pwm resolution (bits) = f cy f pwm ? (timer prescale value) log 10 log 10 (2) bits note 1: based on t cy = t cy /2; doze mode and pll are disabled.
? 2007 microchip technology inc. preliminary ds39881b-page 129 pic24fj64ga004 family example 13-1: pwm period and duty cycle calculations (1) table 13-1: example pwm frequencies and resolutions at 4 mips (f cy = 4 mhz) (1) table 13-2: example pwm frequencies and resolutions at 16 mips (f cy = 16 mhz) (1) pwm frequency 7.6 hz 61 hz 122 hz 977 hz 3.9 khz 31.3 khz 125 khz timer prescaler ratio 8111111 period register value ffffh ffffh 7fffh 0fffh 03ffh 007fh 001fh resolution (bits) 16 16 15 12 10 7 5 note 1: based on t cy = t cy /2; doze mode and pll are disabled. pwm frequency 30.5 hz 244 hz 488 hz 3.9 khz 15.6 khz 125 khz 500 khz timer prescaler ratio 8111111 period register value ffffh ffffh 7fffh 0fffh 03ffh 007fh 001fh resolution (bits) 16 16 15 12 10 7 5 note 1: based on t cy = t cy /2; doze mode and pll are disabled. 1. find the timer period register value for a desired pwm frequency of 52.08 khz, where f osc = 8 mhz with pll (32 mh z device clock rate) and a timer2 prescaler setting of 1:1. t cy = t cy /2 = 62.5 ns pwm period = 1/pwm frequency = 1/52.08 khz = 19.2 s pwm period = (pr2 + 1) ? t cy ? (timer 2 prescale value) 19.2 s = (pr2 + 1) ? 62.5 ns ? 1 pr2 = 306 2. find the maximum resolution of the duty cycle that can be used with a 52.08 khz frequency and a 32 mhz device clock rate: pwm resolution = log 10 (f cy /f pwm )/log 10 2) bits =(log 10 (16 mhz/52.08 khz)/log 10 2) bits = 8.3 bits note 1: based on t cy = t cy /2; doze mode and pll are disabled.
pic24fj64ga004 family ds39881b-page 130 preliminary ? 2007 microchip technology inc. figure 13-1: output comp are module block diagram comparator output logic q s r ocm2:ocm0 output enable ocx (1) set flag bit ocxif (1) ocxrs (1) mode select 3 note 1: where ?x? is shown, reference is made to the register s associated with the respective output compare channels 1 through 5. 2: ocfa pin controls oc1-oc4 channels. ocfb pin controls the oc5 channel. 3: each output compare channel can use one of two selectable time bases. refer to the device data sheet for the time bases associated with the module. 4: this peripheral?s inputs and outputs must be assi gned to an available rpn pin before use. please see section 9.4 ?peripheral pin select? section for more information. octsel 0 1 16 16 ocfa or ocfb (2) tmr register inputs from time bases (see note 3 ). period match signals from time bases (see note 3 ). 0 1 ocxr (1)
? 2007 microchip technology inc. preliminary ds39881b-page 131 pic24fj64ga004 family 13.4 output compare register register 13-1: ocxcon: output compare x control register u-0 u-0 r/w -0 u-0 u-0 u-0 u-0 u-0 ? ?ocsidl ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 r-0, hc r/w -0 r/w -0 r/w -0 r/w -0 ? ? ? ocflt octsel ocm2 (1) ocm1 (1) ocm0 (1) bit 7 bit 0 legend: hc = hardware clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 ocsidl: stop output compare x in idle mode control bit 1 = output compare x will halt in cpu idle mode 0 = output compare x will continue to operate in cpu idle mode bit 12-5 unimplemented: read as ? 0 ? bit 4 ocflt: pwm fault condition status bit 1 = pwm fault condition has occurred (cleared in hw only) 0 = no pwm fault condition has occurred (this bit is only used when ocm<2:0> = 111 ) bit 3 octsel: output compare x timer select bit 1 = timer3 is the clock source for output compare x 0 = timer2 is the clock source for output compare x refer to the device data sheet for specific time bases available to the output compare module. bit 2-0 ocm2:ocm0: output compare x mode select bits (1) 111 = pwm mode on ocx, fault pin, ocfx, enabled (2) 110 = pwm mode on ocx, fault pin, ocfx, disabled (2) 101 = initialize ocx pin low, generate continuous output pulses on ocx pin 100 = initialize ocx pin low, generate single output pulse on ocx pin 011 = compare event toggles ocx pin 010 = initialize ocx pin high, compare event forces ocx pin low 001 = initialize ocx pin low, compare event forces ocx pin high 000 = output compare channel is disabled note 1: rporx (ocx) must be configured to an available rpn pin. for more information, see section 9.4 ?peripheral pin select? . 2: ocfa pin controls oc1-oc4 channels. ocfb pin controls the oc5 channel.
pic24fj64ga004 family ds39881b-page 132 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds39881b-page 133 pic24fj64ga004 family 14.0 serial peripheral interface (spi) the serial peripheral interface (spi) module is a synchronous serial interface useful for communicating with other peripheral or microcontroller devices. these peripheral devices may be serial eeproms, shift reg- isters, display drivers, a/d converters, etc. the spi module is compatible with motorola?s spi and siop interfaces. the module supports operation in two buffer modes. in standard mode, data is shifted through a single serial buffer. in enhanced buffer mode, data is shifted through an 8-level fifo buffer. the module also supports a basic framed spi protocol while operating in either master or slave mode. a total of four framed spi configurations are supported. the spi serial interface consists of four pins: ? sdix: serial data input ? sdox: serial data output ? sckx: shift clock input or output ? ssx : active-low slave select or frame synchronization i/o pulse the spi module can be configured to operate using 2, 3 or 4 pins. in the 3-pin mode, ssx is not used. in the 2-pin mode, both sdox and ssx are not used. block diagrams of the module in standard and enhanced modes are shown in figure 14-1 and figure 14-2. depending on the pin count, devices of the pic24fj64ga004 family offer one or two spi modules on a single device. to set up the spi module for the standard master mode of operation: 1. if using interrupts: a) clear the spixif bit in the respective ifsx register. b) set the spixie bit in the respective iecx register. c) write the spixip bits in the respective ipcx register to set the interrupt priority. 2. write the desired settings to the spixcon register with msten (spixcon1<5>) = 1 . 3. clear the spirov bit (spixstat<6>). 4. enable spi operation by setting the spien bit (spixstat<15>). 5. write the data to be transmitted to the spixbuf register. transmission (and reception) will start as soon as data is written to the spixbuf register. to set up the spi module for the standard slave mode of operation: 1. clear the spixbuf register. 2. if using interrupts: a) clear the spixif bit in the respective ifsx register. b) set the spixie bit in the respective iecx register. c) write the spixip bits in the respective ipcx register to set the interrupt priority. 3. write the desired settings to the spixcon1 and spixcon2 registers with msten (spixcon1<5>) = 0 . 4. clear the smp bit. 5. if the cke bit is set, then the ssen bit (spixcon1<7>) must be set to enable the ssx pin. 6. clear the spirov bit (spixstat<6>). 7. enable spi operation by setting the spien bit (spixstat<15>). note 1: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the associated ?pic24f family reference manual? chapter. 2: this peripheral contains input functions that may need to be configured by the peripheral pin select feature. for more information, see section 9.4 ?peripheral pin select? . note: do not perform read-modify-write opera- tions (such as bit-oriented instructions) on the spixbuf register in either standard or enhanced buffer mode. note: in this section, the spi modules are referred to together as spix or separately as spi1 and spi2. special function reg- isters will follow a similar notation. for example, spixcon refers to the control register for the spi1 or spi2 module.
pic24fj64ga004 family ds39881b-page 134 preliminary ? 2007 microchip technology inc. to set up the spi module for the enhanced buffer master mode of operation: 1. if using interrupts: a) clear the spixif bit in the respective ifsx register. b) set the spixie bit in the respective iecx register. c) write the spixip bits in the respective ipcx register. 2. write the desired settings to the spixcon1 and spixcon2 registers with msten (spixcon1<5>) = 1 . 3. clear the spirov bit (spixstat<6>). 4. select enhanced buffer mode by setting the spiben bit (spixcon2<0>). 5. enable spi operation by setting the spien bit (spixstat<15>). 6. write the data to be transmitted to the spixbuf register. transmission (and reception) will start as soon as data is written to the spixbuf register. to set up the spi module for the enhanced buffer slave mode of operation: 1. clear the spixbuf register. 2. if using interrupts: ? clear the spixif bit in the respective ifsx register. ? set the spixie bit in the respective iecx register. ? write the spixip bits in the respective ipcx register to set the interrupt priority. 3. write the desired settings to the spixcon1 and spixcon2 registers with msten (spixcon1<5>) = 0 . 4. clear the smp bit. 5. if the cke bit is set, then the ssen bit must be set, thus enabling the ssx pin. 6. clear the spirov bit (spixstat<6>). 7. select enhanced buffer mode by setting the spiben bit (spixcon2<0>). 8. enable spi operation by setting the spien bit (spixstat<15>). figure 14-1: spix module block diagram (standard mode) internal data bus sdix sdox ssx /fsyncx sckx spixsr bit 0 shift control edge select f cy primary 1:1/4/16/64 enable prescaler sync clock control spixbuf control transfer transfer write spixbuf read spixbuf 16 spixcon1<1:0> spixcon1<4:2> master clock secondary prescaler 1:1 to 1:8
? 2007 microchip technology inc. preliminary ds39881b-page 135 pic24fj64ga004 family figure 14-2: spix module bl ock diagram (enhanced mode) internal data bus sdix sdox ssx /fsyncx sckx spixsr bit0 shift control edge select f cy primary 1:1/4/16/64 enable prescaler secondary prescaler 1:1 to 1:8 sync clock control spixbuf control transfer transfer write spixbuf read spixbuf 16 spixcon1<1:0> spixcon1<4:2> master clock 8-level fifo transmit buffer 8-level fifo receive buffer
pic24fj64ga004 family ds39881b-page 136 preliminary ? 2007 microchip technology inc. register 14-1: spixstat: spix status and control register r/w -0 u-0 r/w -0 u-0 u-0 r-0 r-0 r-0 spien (1) ? spisidl ? ? spibec2 spibec1 spibec0 bit 15 bit 8 r-0 r/c-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 srmpt spirov srxmpt sisel2 sisel1 sisel0 spitbf spirbf bit 7 bit 0 legend: c = clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 spien: spix enable bit (1) 1 = enables module and configures sckx, sdox, sdix and ssx as serial port pins 0 = disables module bit 14 unimplemented: read as ? 0 ? bit 13 spisidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-11 unimplemented: read as ? 0 ? bit 10-8 spibec2:spibec0: spix buffer element count bits (valid in enhanced buffer mode) master mode: number of spi transfers pending. slave mode: number of spi transfers unread. bit 7 srmpt: shift register (spixsr) empty bit (valid in enhanced buffer mode) 1 = spix shift register is empty and ready to send or receive 0 = spix shift register is not empty bit 6 spirov: receive overflow flag bit 1 = a new byte/word is completely received and disc arded. the user software has not read the previous data in the spixbuf register. 0 = no overflow has occurred bit 5 srxmpt: receive fifo empty bit (valid in enhanced buffer mode) 1 = receive fifo is empty 0 = receive fifo is not empty bit 4-2 sisel2:sisel0: spix buffer interrupt mode bits (valid in enhanced buffer mode) 111 = interrupt when spix transmit buffer is full (spitbf bit is set) 110 = interrupt when last bit is shifted into spixsr, as a result, the tx fifo is empty 101 = interrupt when the last bit is shifted out of spixsr, now the transmit is complete 100 = interrupt when one data is shifted into the spixsr, as a result, the tx fifo has one open spot 011 = interrupt when spix receive buffer is full (spirbf bit set) 010 = interrupt when spix receive buffer is 3/4 or more full 001 = interrupt when data is available in receive buffer (srmpt bit is set) 000 = interrupt when the last data in the receive buffer is read, as a result, the buffer is empty (srxmpt bit set) note 1: if spien = 1 , these functions must be assigned to available rpn pins before use. see section 9.4 ?peripheral pin select? for more information.
? 2007 microchip technology inc. preliminary ds39881b-page 137 pic24fj64ga004 family bit 1 spitbf: spix transmit buffer full status bit 1 = transmit not yet started, spixtxb is full 0 = transmit started, spixtxb is empty in standard buffer mode: automatically set in hardware when cpu writes spixbuf location, loading spixtxb. automatically cleared in hardware when spix module transfers data from spixtxb to spixsr. in enhanced buffer mode: automatically set in hardware when cpu writes spixbuf location, loading the last available buffer location. automatically cleared in hardware when a buffer location is available for a cpu write. bit 0 spirbf: spix receive buffer full status bit 1 = receive complete, spixrxb is full 0 = receive is not complete, spixrxb is empty in standard buffer mode: automatically set in hardware when spix transfers data from spixsr to spixrxb. automatically cleared in hardware when core reads spixbuf location, reading spixrxb. in enhanced buffer mode: automatically set in hardware when spix transfers data from spixsr to buffer, filling the last unread buffer location. automatically cleared in hardware when a buffer location is available for a transfer from spixsr. register 14-1: spixstat: spix status and control register (continued) note 1: if spien = 1 , these functions must be assigned to available rpn pins before use. see section 9.4 ?peripheral pin select? for more information.
pic24fj64ga004 family ds39881b-page 138 preliminary ? 2007 microchip technology inc. register 14-2: spi x con1: spix control register 1 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ? dissck (1) dissdo (2) mode16 smp cke (3) bit 15 bit 8 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ssen (4) ckp msten spre2 spre1 spre0 ppre1 ppre0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12 dissck: disable sckx pin bit (spi master modes only) (1) 1 = internal spi clock is disabled; pin functions as i/o 0 = internal spi clock is enabled bit 11 dissdo: disable sdox pin bit (2) 1 = sdox pin is not used by module; pin functions as i/o 0 = sdox pin is controlled by the module bit 10 mode16: word/byte communication select bit 1 = communication is word-wide (16 bits) 0 = communication is byte-wide (8 bits) bit 9 smp: spix data input sample phase bit master mode: 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time slave mode: smp must be cleared when spix is used in slave mode. bit 8 cke: spix clock edge select bit (3) 1 = serial output data changes on transition from active clock state to idle clock state (see bit 6) 0 = serial output data changes on transition from idle clock state to active clock state (see bit 6) bit 7 ssen: slave select enable (slave mode) bit (4) 1 = ssx pin used for slave mode 0 = ssx pin not used by module; pin controlled by port function bit 6 ckp: clock polarity select bit 1 = idle state for clock is a high level; active state is a low level 0 = idle state for clock is a low level; active state is a high level bit 5 msten: master mode enable bit 1 = master mode 0 =slave mode note 1: if dissck = 0 , sckx must be configured to an available rpn pin. see section 9.4 ?peripheral pin select? for more information. 2: if dissdo = 0 , sdox must be configured to an available rpn pin. see section 9.4 ?peripheral pin select? for more information. 3: the cke bit is not used in the framed spi modes. the user should program this bit to ? 0 ? for the framed spi modes (frmen = 1 ). 4: if ssen = 1 , ssx must be configured to an available rpn pin. see section 9.4 ?peripheral pin select? for more information.
? 2007 microchip technology inc. preliminary ds39881b-page 139 pic24fj64ga004 family bit 4-2 spre2:spre0: secondary prescale bits (master mode) 111 = secondary prescale 1:1 110 = secondary prescale 2:1 ... 000 = secondary prescale 8:1 bit 1-0 ppre1:ppre0: primary prescale bits (master mode) 11 = primary prescale 1:1 10 = primary prescale 4:1 01 = primary prescale 16:1 00 = primary prescale 64:1 register 14-2: spi x con1: spix control register 1 (continued) note 1: if dissck = 0 , sckx must be configured to an available rpn pin. see section 9.4 ?peripheral pin select? for more information. 2: if dissdo = 0 , sdox must be configured to an available rpn pin. see section 9.4 ?peripheral pin select? for more information. 3: the cke bit is not used in the framed spi modes. the user should program this bit to ? 0 ? for the framed spi modes (frmen = 1 ). 4: if ssen = 1 , ssx must be configured to an available rpn pin. see section 9.4 ?peripheral pin select? for more information. register 14-3: spixcon2: spix control register 2 r/w -0 r/w -0 r/w -0 u-0 u-0 u-0 u-0 u-0 frmen spifsd spifpol ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w -0 r/w -0 ? ? ? ? ? ? spife spiben bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 frmen: framed spix support bit 1 = framed spix support enabled 0 = framed spix support disabled bit 14 spifsd: frame sync pulse direction control on ssx pin bit 1 = frame sync pulse input (slave) 0 = frame sync pulse output (master) bit 13 spifpol: frame sync pulse polarity bit (frame mode only) 1 = frame sync pulse is active-high 0 = frame sync pulse is active-low bit 12-2 unimplemented: read as ? 0 ? bit 1 spife: frame sync pulse edge select bit 1 = frame sync pulse coincides with first bit clock 0 = frame sync pulse precedes first bit clock bit 0 spiben: enhanced buffer enable bit 1 = enhanced buffer enabled 0 = enhanced buffer disabled (legacy mode)
pic24fj64ga004 family ds39881b-page 140 preliminary ? 2007 microchip technology inc. figure 14-3: spi master/slave connection (standard mode) figure 14-4: spi master/slave connection (enhanced buffer modes) serial receive buffer (spixrxb) shift register (spixsr) lsb msb sdix sdox processor 2 (spi slave) sckx ssx serial transmit buffer (spixtxb) serial receive buffer (spixrxb) shift register (spixsr) msb lsb sdox sdix processor 1 (spi master) serial clock ssen (spixcon1<7>) = 1 and msten (spixcon1<5>) = 0 note 1: using the ssx pin in slave mode of operation is optional. 2: user must write transmit data to read received data from spixbuf. the spixtxb and spixrxb registers are memory mapped to spixbuf. sckx serial transmit buffer (spixtxb) msten (spixcon1<5>) = 1 ) spix buffer (spixbuf) spix buffer (spixbuf) shift register (spixsr) lsb msb sdix sdox processor 2 (spi enhanced buffer slave) sckx ssx shift register (spixsr) msb lsb sdox sdix processor 1 (spi enha nced buffer master) serial clock ssen (spixcon1<7>) = 1 , note 1: using the ssx pin in slave mode of operation is optional. 2: user must write transmit data to read received data from spixbuf. the spixtxb and spixrxb registers are memory mapped to spixbuf. ssx sckx 8-level fifo buffer msten (spixcon1<5>) = 1 and spix buffer (spixbuf) 8-level fifo buffer spix buffer (spixbuf) spiben (spixcon2<0>) = 1 msten (spixcon1<5>) = 0 and spiben (spixcon2<0>) = 1
? 2007 microchip technology inc. preliminary ds39881b-page 141 pic24fj64ga004 family figure 14-5: spi master, frame master connection diagram figure 14-6: spi master, frame slave connection diagram figure 14-7: spi slave, frame master connection diagram figure 14-8: spi slave, frame slave connection diagram sdox sdix pic24f serial clock ssx sckx frame sync pulse sdix sdox processor 2 ssx sckx (spi slave, frame slave) sdox sdix pic24f serial clock ssx sckx frame sync pulse sdix sdox processor 2 ssx sckx spi master, frame slave) sdox sdix pic24f serial clock ssx sckx frame sync. pulse sdix sdox processor 2 ssx sckx (spi slave, frame slave) sdox sdix pic24f serial clock ssx sckx frame sync pulse sdix sdox processor 2 ssx sckx (spi master, frame slave)
pic24fj64ga004 family ds39881b-page 142 preliminary ? 2007 microchip technology inc. equation 14-1: relationship between device and spi clock speed (1) table 14-1: sample sck frequencies (1,2) f cy = 16 mhz secondary prescaler settings 1:12:14:16:18:1 primary prescaler settings 1:1 invalid 8000 4000 2667 2000 4:1 4000 2000 1000 667 500 16:1 1000 500 250 167 125 64:1 250 125 63 42 31 f cy = 5 mhz primary prescaler settings 1:1 5000 2500 1250 833 625 4:1 1250 625 313 208 156 16:1 313 156 78 52 39 64:17839201310 note 1: based on t cy = t cy /2; doze mode and pll are disabled. 2: sckx frequencies shown in khz. primary prescaler * secondary prescaler f cy f sck = note 1: based on t cy = t cy /2; doze mode and pll are disabled.
? 2007 microchip technology inc. preliminary ds39881b-page 143 pic24fj64ga004 family 15.0 inter-integrated circuit (i 2 c?) the inter-integrated circuit (i 2 c) module is a serial interface useful for communicating with other periph- eral or microcontroller devices. these peripheral devices may be serial eeproms, display drivers, a/d converters, etc. the i 2 c module supports these features: ? independent master and slave logic ? 7-bit and 10-bit device addresses ? general call address, as defined in the i 2 c protocol ? clock stretching to provide delays for the processor to respond to a slave data request ? both 100 khz and 400 khz bus specifications. ? configurable address masking ? multi-master modes to prevent loss of messages in arbitration ? bus repeater mode, allowing the acceptance of all messages as a slave regardless of the address ? automatic scl a block diagram of the module is shown in figure 15-1. 15.1 communicating as a master in a single master environment the details of sending a message in master mode depends on the communications protocol for the device being communicated with. typically, the sequence of events is as follows: 1. assert a start condition on sdax and sclx. 2. send the i 2 c device address byte to the slave with a write indication. 3. wait for and verify an acknowledge from the slave. 4. send the first data byte (sometimes known as the command) to the slave. 5. wait for and verify an acknowledge from the slave. 6. send the serial memory address low byte to the slave. 7. repeat steps 4 and 5 until all data bytes are sent. 8. assert a repeated start condition on sdax and sclx. 9. send the device address byte to the slave with a read indication. 10. wait for and verify an acknowledge from the slave. 11. enable master reception to receive serial memory data. 12. generate an ack or nack condition at the end of a received byte of data. 13. generate a stop condition on sdax and sclx. note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the associated ?pic24f family reference manual? chapter.
pic24fj64ga004 family ds39881b-page 144 preliminary ? 2007 microchip technology inc. figure 15-1: i 2 c? block diagram i2cxrcv internal data bus sclx sdax shift match detect i2cxadd start and stop bit detect clock address match clock stretching i2cxtrn lsb shift clock brg down counter reload control t cy /2 start and stop bit generation acknowledge generation collision detect i2cxcon i2cxstat control logic read lsb write read i2cxbrg i2cxrsr write read write read write read write read write read i2cxmsk
? 2007 microchip technology inc. preliminary ds39881b-page 145 pic24fj64ga004 family 15.2 setting baud rate when operating as a bus master to compute the baud rate generator reload value, use equation 15-1. equation 15-1: computing baud rate reload value (1) 15.3 slave address masking the i2cxmsk register (register 15-3) designates address bit positions as ?don?t care? for both 7-bit and 10-bit addressing modes. setting a particular bit loca- tion (= 1 ) in the i2cxmsk register causes the slave module to respond whether the corresponding address bit value is a ? 0 ? or a ? 1 ?. for example, when i2cxmsk is set to ? 00100000 ?, the slave module will detect both addresses, ? 0000000 ? and ? 00100000 ?. to enable address masking, the ipmi (intelligent peripheral management interface) must be disabled by clearing the ipmien bit (i2cxcon<11>). 15.3.1 peripheral pin select limitations the i2c1 has limited peripheral pin select capability. the sda1/scl1 pins have alternative multiplexing based on the setting of the i2c1sel bit. the default pins are used when the bit is set. table 15-1: i 2 c? clock rates (1) i2cxbrg f cy 2f scl ? ------------------- ?? ?? 1 ? = f scl f cy 2i2cxbrg1 + () ? --------------------------------------------- - = or note 1: based on t cy = t cy /2; doze mode and pll are disabled. note: the i2c1sel bit is a configuration bit in the flash configuration word. it is not part of the regular device configuration regis- ters. for more information, see section 3.1.3 ?flash configuration words? . required system f scl f cy i2cxbrg value actual f scl (decimal) (hexadecimal) 100 khz 16 mhz 79 4f 100 khz 100 khz 8 mhz 39 27 100 khz 100 khz 4 mhz 19 13 100 khz 400 khz 16 mhz 19 13 400 khz 400khz 8mhz 9 9 400khz 400khz 4mhz 4 4 400khz 400 khz 2 mhz 2 2 333 khz (2) 1mhz 16mhz 7 7 1mhz 1 mhz 8 mhz 3 3 1 mhz (3) 1mhz 4mhz 1 1 1mhz (4) legend: shaded rows represent invalid reload values for a given f scl and f cy . note 1: based on t cy = t cy /2, doze mode and pll are disabled. 2: this is the closest value to 400 khz for this value of f cy . 3: f cy = 2 mhz is the minimum input clock frequency to have f scl = 1 mhz. 4: i2cxbrg cannot have a value of less than 2. note: to comply with i 2 c? definition, the addresses in table 15-2 on page 146 are reserved and will not be acknowledged by the i 2 c peripheral operating in slave mode.
pic24fj64ga004 family ds39881b-page 146 preliminary ? 2007 microchip technology inc. table 15-2: i 2 c? reserved addresses (1) slave address r/w bit description 0000 000 0 general call address (2) 0000 000 1 start byte 0000 001 x cbus address 0000 010 x reserved 0000 011 x reserved 0000 1xx x hs mode master code 1111 1xx x reserved 1111 0xx x 10-bit slave upper byte (3) note 1: the above address bits will never cause an address match, independent of address mask settings. 2: address will be acknowledged only if gcen = 1 . 3: match on this address can only occur on the upper byte in 10-bit addressing mode.
? 2007 microchip technology inc. preliminary ds39881b-page 147 pic24fj64ga004 family register 15-1: i2cxcon: i2cx control register r/w -0 u-0 r/w -0 r/w -1 hc r/w -0 r/w -0 r/w -0 r/w -0 i2cen ? i2csidl sclrel ipmien a10m disslw smen bit 15 bit 8 r/w -0 r/w -0 r/w -0 r/w -0, hc r/w -0, hc r/w -0, hc r/w -0, hc r/w -0, hc gcen stren ackdt acken rcen pen rsen sen bit 7 bit 0 legend: hc = hardware clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 i2cen: i2cx enable bit 1 = enables the i2cx module and configures the sdax and sclx pins as serial port pins 0 = disables i2cx module. all i 2 c pins are controlled by port functions. bit 14 unimplemented: read as ? 0 ? bit 13 i2csidl: stop in idle mode bit 1 = discontinues module operation when device enters an idle mode 0 = continues module operation in idle mode bit 12 sclrel: sclx release control bit (when operating as i 2 c slave) 1 = releases sclx clock 0 = holds sclx clock low (clock stretch) if stren = 1 : bit is r/w (i.e., software may write ? 0 ? to initiate stretch and write ? 1 ? to release clock). hardware clear at beginning of slave transmission. hardware clear at end of slave reception. if stren = 0 : bit is r/s (i.e., software may only write ? 1 ? to release clock). hardware clear at beginning of slave transmission. bit 11 ipmien: intelligent peripheral management interface (ipmi) enable bit 1 = ipmi support mode is enabled; all addresses acknowledged 0 = ipmi mode disabled bit 10 a10m: 10-bit slave addressing bit 1 = i2cxadd is a 10-bit slave address 0 = i2cxadd is a 7-bit slave address bit 9 disslw: disable slew rate control bit 1 = slew rate control disabled 0 = slew rate control enabled bit 8 smen: smbus input levels bit 1 = enables i/o pin thresholds compliant with smbus specification 0 = disables smbus input thresholds bit 7 gcen: general call enable bit (when operating as i 2 c slave) 1 = enables interrupt when a general call address is received in the i2cxrsr (module is enabled for reception) 0 = general call address disabled bit 6 stren: sclx clock stretch enable bit (when operating as i 2 c slave) used in conjunction with sclrel bit. 1 = enables software or receive clock stretching 0 = disables software or receive clock stretching
pic24fj64ga004 family ds39881b-page 148 preliminary ? 2007 microchip technology inc. bit 5 ackdt: acknowledge data bit (when operating as i 2 c master. applicable during master receive.) value that will be transmitted when the software initiates an acknowledge sequence. 1 = sends nack during acknowledge 0 = sends ack during acknowledge bit 4 acken: acknowledge sequence enable bit (when operating as i 2 c master. applicable during master receive.) 1 = initiates acknowledge sequence on sdax and sclx pins and transmits ackdt data bit. hardware clear at end of master acknowledge sequence. 0 = acknowledge sequence not in progress bit 3 rcen: receive enable bit (when operating as i 2 c master) 1 = enables receive mode for i 2 c. hardware clear at end of eighth bit of master receive data byte. 0 = receives sequence not in progress bit 2 pen: stop condition enable bit (when operating as i 2 c master) 1 = initiates stop condition on sdax and sclx pins. hardware clear at end of master stop sequence. 0 = stop condition not in progress bit 1 rsen: repeated start condition enabled bit (when operating as i 2 c master) 1 = initiates repeated start condition on sdax and sclx pins. hardware clear at end of master repeated start sequence. 0 = repeated start condition not in progress bit 0 sen: start condition enabled bit (when operating as i 2 c master) 1 = initiates start condition on sdax and sclx pins. hardware clear at end of master start sequence. 0 = start condition not in progress register 15-1: i2cxcon: i2cx control register (continued)
? 2007 microchip technology inc. preliminary ds39881b-page 149 pic24fj64ga004 family register 15-2: i2cxstat: i2cx status register r-0, hsc r-0, hsc u-0 u-0 u-0 r/c-0, hs r-0, hsc r-0, hsc ackstat trstat ? ? ? bcl gcstat add10 bit 15 bit 8 r/c-0, hs r/c-0, hs r-0, hsc r/c-0, hsc r/c-0, hsc r-0, hsc r-0, hsc r-0, hsc iwcol i2cov d/a psr/w rbf tbf bit 7 bit 0 legend: c = clearable bit hs = hardware set bit hsc = hardware set, cleared bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ackstat: acknowledge status bit 1 = nack was detected last 0 = ack was detected last hardware set or clear at end of acknowledge. bit 14 trstat: transmit status bit (when operating as i 2 c master. applicable to master transmit operation.) 1 = master transmit is in progress (8 bits + ack) 0 = master transmit is not in progress hardware set at beginning of master transmission. hardware clear at end of slave acknowledge. bit 13-11 unimplemented: read as ? 0 ? bit 10 bcl: master bus collision detect bit 1 = a bus collision has been detected during a master operation 0 = no collision hardware set at detection of bus collision. bit 9 gcstat: general call status bit 1 = general call address was received 0 = general call address was not received hardware set when address matches general call address. hardware clear at stop detection. bit 8 add10: 10-bit address status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched hardware set at match of 2nd byte of matched 10-bit address. hardware clear at stop detection. bit 7 iwcol: write collision detect bit 1 = an attempt to write the i2cxtrn register failed because the i 2 c module is busy 0 = no collision hardware set at occurrence of write to i2cxtrn while busy (cleared by software). bit 6 i2cov: receive overflow flag bit 1 = a byte was received while the i2cxrcv register is still holding the previous byte 0 = no overflow hardware set at attempt to transfer i2cxrsr to i2cxrcv (cleared by software). bit 5 d/a : data/address bit (when operating as i 2 c slave) 1 = indicates that the last byte received was data 0 = indicates that the last byte received was device address hardware clear at device address match. hardware set by write to i2cxtrn or by reception of slave byte.
pic24fj64ga004 family ds39881b-page 150 preliminary ? 2007 microchip technology inc. bit 4 p: stop bit 1 = indicates that a stop bit has been detected last 0 = stop bit was not detected last hardware set or clear when start, repeated start or stop detected. bit 3 s: start bit 1 = indicates that a start (or repeated start) bit has been detected last 0 = start bit was not detected last hardware set or clear when start, repeated start or stop detected. bit 2 r/w : read/write information bit (when operating as i 2 c slave) 1 = read ? indicates data transfer is output from slave 0 = write ? indicates data transfer is input to slave hardware set or clear after reception of i 2 c device address byte. bit 1 rbf: receive buffer full status bit 1 = receive complete, i2cxrcv is full 0 = receive not complete, i2cxrcv is empty hardware set when i2cxrcv is written with received byte. hardware clear when software reads i2cxrcv. bit 0 tbf: transmit buffer full status bit 1 = transmit in progress, i2cxtrn is full 0 = transmit complete, i2cxtrn is empty hardware set when software writes i2cxtrn. hardware clear at completion of data transmission. register 15-2: i2cxstat: i2cx status register (continued)
? 2007 microchip technology inc. preliminary ds39881b-page 151 pic24fj64ga004 family register 15-3: i2cxmsk: i2cx slave mode address mask register u-0 u-0 u-0 u-0 u-0 u-0 r/w -0 r/w -0 ? ? ? ? ? ? amsk9 amsk8 bit 15 bit 8 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 amsk7 amsk6 amsk5 amsk4 amsk3 amsk2 amsk1 amsk0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-10 unimplemented: read as ? 0 ? bit 9-0 amsk9:amsk0: mask for address bit x select bits 1 = enable masking for bit x of incoming message address; bit match not required in this position 0 = disable masking for bit x; bit match required in this position
pic24fj64ga004 family ds39881b-page 152 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds39881b-page 153 pic24fj64ga004 family 16.0 universal asynchronous receiver transmitter (uart) the universal asynchronous receiver transmitter (uart) module is one of the serial i/o modules available in the pic24f device family. the uart is a full-duplex asynchronous system that can communi- cate with peripheral devices, such as personal comput- ers, lin, rs-232 and rs-485 interfaces. the module also supports a hardware flow control option with the uxcts and uxrts pins and also includes an irda ? encoder and decoder. the primary features of the uart module are: ? full-duplex, 8 or 9-bit data transmission through the uxtx and uxrx pins ? even, odd or no parity options (for 8-bit data) ? one or two stop bits ? hardware flow control option with uxcts and uxrts pins ? fully integrated baud rate generator with 16-bit prescaler ? baud rates ranging from 1 mbps to 15 bps at 16 mips ? 4-deep, first-in-first-out (fifo) transmit data buffer ? 4-deep fifo receive data buffer ? parity, framing and buffer overrun error detection ? support for 9-bit mode with address detect (9th bit = 1 ) ? transmit and receive interrupts ? loopback mode for diagnostic support ? support for sync and break characters ? supports automatic baud rate detection ? irda encoder and decoder logic ? 16x baud clock output for irda support a simplified block diagram of the uart is shown in figure 16-1. the uart module consists of these key important hardware elements: ? baud rate generator ? asynchronous transmitter ? asynchronous receiver figure 16-1: uart simplified block diagram note 1: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the associated ?pic24f family reference manual? chapter. 2: this peripheral contains input and output functions that may need to be configured by the peripheral pin select feature. for more information, see section 9.4 ?peripheral pin select? . uxrx irda ? hardware flow control uartx receiver uartx transmitter uxtx uxcts uxrts bclkx baud rate generator note: this peripheral?s inputs and outputs must be assigned to an available rpn pin before use. please see section 9.4 ?peripheral pin select? for more information.
pic24fj64ga004 family ds39881b-page 154 preliminary ? 2007 microchip technology inc. 16.1 uart baud rate generator (brg) the uart module includes a dedicated 16-bit baud rate generator. the uxbrg register controls the period of a free-running, 16-bit timer. equation 16-1 shows the formula for computation of the baud rate with brgh = 0 . equation 16-1: uart baud rate with brgh = 0 (1,2) example 16-1 shows the calculation of the baud rate error for the following conditions: ?f cy = 4 mhz ? desired baud rate = 9600 the maximum baud rate (brgh = 0 ) possible is f cy /16 (for uxbrg = 0 ) and the minimum baud rate possible is f cy /(16 * 65536). equation 16-2 shows the formula for computation of the baud rate with brgh = 1 . equation 16-2: uart baud rate with brgh = 1 (1,2) the maximum baud rate (brgh = 1 ) possible is f cy /4 (for uxbrg = 0 ) and the minimum baud rate possible is f cy /(4 * 65536). writing a new value to the uxbrg register causes the brg timer to be reset (cleared). this ensures the brg does not wait for a timer overflow before generating the new baud rate. example 16-1: baud rate error calculation (brgh = 0 ) (1) note 1: f cy denotes the instruction cycle clock frequency (f osc /2 ). 2: based on t cy = t cy /2; doze mode and pll are disabled. baud rate = f cy 16 ? (uxbrg + 1) f cy 16 ? baud rate uxbrg = ? 1 baud rate = f cy 4 ? (uxbrg + 1) f cy 4 ? baud rate uxbrg = ? 1 note 1: f cy denotes the instruction cycle clock frequency . 2: based on t cy = t cy /2; doze mode and pll are disabled. desired baud rate = f cy /(16 (uxbrg + 1)) solving for uxbrg value: uxbrg = ((f cy /desired baud rate)/16) ? 1 uxbrg = ((4000000/9600)/16) ? 1 uxbrg = 25 calculated baud rate= 4000000/(16 (25 + 1)) = 9615 error = (calculated baud ra te ? desired baud rate) desired baud rate = (9615 ? 9600)/9600 = 0.16% note 1: based on t cy = t cy /2; doze mode and pll are disabled.
? 2007 microchip technology inc. preliminary ds39881b-page 155 pic24fj64ga004 family 16.2 transmitting in 8-bit data mode 1. set up the uart: a) write appropriate values for data, parity and stop bits. b) write appropriate baud rate value to the uxbrg register. c) set up transmit and receive interrupt enable and priority bits. 2. enable the uart. 3. set the utxen bit (causes a transmit interrupt). 4. write data byte to lower byte of uxtxreg word. the value will be immediately transferred to the transmit shift register (tsr), and the serial bit stream will start shifting out with next rising edge of the baud clock. 5. alternately, the data byte may be transferred while utxen = 0 , and then the user may set utxen. this will cause the serial bit stream to begin immediately because the baud clock will start from a cleared state. 6. a transmit interrupt will be generated as per interrupt control bit, utxiselx. 16.3 transmitting in 9-bit data mode 1. set up the uart (as described in section 16.2 ?transmitting in 8-bit data mode? ). 2. enable the uart. 3. set the utxen bit (causes a transmit interrupt). 4. write uxtxreg as a 16-bit value only. 5. a word write to uxtxreg triggers the transfer of the 9-bit data to the tsr. serial bit stream will start shifting out with the first rising edge of the baud clock. 6. a transmit interrupt will be generated as per the setting of control bit, utxiselx. 16.4 break and sync transmit sequence the following sequence will send a message frame header made up of a break, followed by an auto-baud sync byte. 1. configure the uart for the desired mode. 2. set utxen and utxbrk ? sets up the break character. 3. load the uxtxreg with a dummy character to initiate transmission (value is ignored). 4. write ?55h? to uxtxreg ? loads sync character into the transmit fifo. 5. after the break has been sent, the utxbrk bit is reset by hardware. the sync character now transmits. 16.5 receiving in 8-bit or 9-bit data mode 1. set up the uart (as described in section 16.2 ?transmitting in 8-bit data mode? ). 2. enable the uart. 3. a receive interrupt will be generated when one or more data characters have been received as per interrupt control bit, urxiselx. 4. read the oerr bit to determine if an overrun error has occurred. the oerr bit must be reset in software. 5. read uxrxreg. the act of reading the uxrxreg character will move the next character to the top of the receive fifo, including a new set of perr and ferr values. 16.6 operation of ux cts and ux rts control pins uartx clear to send (ux cts ) and request to send (ux rts ) are the two hardware controlled pins that are associated with the uart module. these two pins allow the uart to operate in simplex and flow control mode. they are implemented to control the transmis- sion and reception between the data terminal equipment (dte). the uen<1:0> bits in the uxmode register configure these pins. 16.7 infrared support the uart module provides two types of infrared uart support: one is the irda clock output to support exter- nal irda encoder and decoder device (legacy module support) and the other is the full implementation of the irda encoder and decoder. note that because the irda modes require a 16x baud clock, they will only work when the brgh bit (uxmode<3>) is ? 0 ?. 16.8 external irda support ? irda clock output to support external irda encoder and decoder devices, the bclkx pin (same as the ux rts pin) can be configured to generate the 16x baud clock. with uen<1:0> = 11 , the bclkx pin will output the 16x baud clock if the uart module is enabled. it can be used to support the irda codec chip. 16.9 built-in irda encoder and decoder the uart has full implementation of the irda encoder and decoder as part of the uart module. the built-in irda encoder and decoder functionality is enabled using the iren bit (uxmode<12>). when enabled (iren = 1 ), the receive pin (uxrx) acts as the input from the infrared receiver. the transmit pin (uxtx) acts as the output to the infrared transmitter.
pic24fj64ga004 family ds39881b-page 156 preliminary ? 2007 microchip technology inc. register 16-1: uxmode: uartx mode register r/w -0 u-0 r/w -0 r/w -0 r/w -0 u-0 r/w -0 (3) r/w -0 (3) uarten (1) ? usidl iren (2) rtsmd ?uen1uen0 bit 15 bit 8 r/c-0, hc r/w -0 r/w -0, hc r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 wake lpback abaud rxinv brgh pdsel1 pdsel0 stsel bit 7 bit 0 legend: c = cleared bit hc = hardware clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 uarten: uartx enable bit (1) 1 = uartx is enabled; all uartx pins are controlled by uartx as defined by uen<1:0> 0 = uartx is disabled; all uartx pins are controlled by port latches; uartx power consumption minimal bit 14 unimplemented: read as ? 0 ? bit 13 usidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12 iren: irda ? encoder and decoder enable bit (2) 1 = irda encoder and decoder enabled 0 = irda encoder and decoder disabled bit 11 rtsmd: mode selection for uxrts pin bit 1 =uxrts pin in simplex mode 0 =uxrts pin in flow control mode bit 10 unimplemented: read as ? 0 ? bit 9-8 uen1:uen0: uartx enable bits (3) 11 = uxtx, uxrx and bclkx pins are enabled and used; uxcts pin controlled by port latches 10 = uxtx, uxrx, uxcts and uxrts pins are enabled and used 01 = uxtx, uxrx and uxrts pins are enabled and used; uxcts pin controlled by port latches 00 = uxtx and uxrx pins are enabled and used; uxcts and uxrts /bclkx pins controlled by port latches bit 7 wake: wake-up on start bit detect during sleep mode enable bit 1 = uartx will continue to sample the uxrx pin; interrupt generated on falling edge, bit cleared in hardware on following rising edge 0 = no wake-up enabled bit 6 lpback: uartx loopback mode select bit 1 = enable loopback mode 0 = loopback mode is disabled bit 5 abaud: auto-baud enable bit 1 = enable baud rate measurement on the next character ? requires reception of a sync field (55h); cleared in hardware upon completion 0 = baud rate measurement disabled or completed note 1: if uarten = 1 , the peripheral inputs and outputs must be configured to an available rpn pin. see section 9.4 ?peripheral pin select? for more information. 2: this feature is only available for the 16x brg mode (brgh = 0 ). 3: bit availability depends on pin availability.
? 2007 microchip technology inc. preliminary ds39881b-page 157 pic24fj64ga004 family bit 4 rxinv: receive polarity inversion bit 1 = uxrx idle state is ? 0 ? 0 = uxrx idle state is ? 1 ? bit 3 brgh: high baud rate enable bit 1 = brg generates 4 clocks per bit period (4x baud clock, high-speed mode) 0 = brg generates 16 clocks per bit period (16x baud clock, standard mode) bit 2-1 pdsel1:pdsel0: parity and data selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 stsel: stop bit selection bit 1 = two stop bits 0 = one stop bit register 16-1: uxmode: uartx mode register (continued) note 1: if uarten = 1 , the peripheral inputs and outputs must be configured to an available rpn pin. see section 9.4 ?peripheral pin select? for more information. 2: this feature is only available for the 16x brg mode (brgh = 0 ). 3: bit availability depends on pin availability.
pic24fj64ga004 family ds39881b-page 158 preliminary ? 2007 microchip technology inc. register 16-2: uxsta: uartx status and control register r/w -0 r/w -0 r/w -0 u-0 r/w -0 hc r/w -0 r-0 r-1 utxisel1 utxinv (1) utxisel0 ? utxbrk utxen (2) utxbf trmt bit 15 bit 8 r/w -0 r/w -0 r/w -0 r-1 r-0 r-0 r/c-0 r-0 urxisel1 urxisel0 adden ridle perr ferr oerr urxda bit 7 bit 0 legend: c = clearable bit hc = hardware clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15,13 utxisel1:utxisel0: transmission interrupt mode selection bits 11 = reserved; do not use 10 = interrupt when a character is transferred to the transmit shift register (tsr) and as a result, the transmit buffer becomes empty 01 = interrupt when the last character is shifted out of the transmit shift register; all transmit operations are completed 00 = interrupt when a character is transferred to the transmit shift register (this implies there is at least one character open in the transmit buffer) bit 14 utxinv: irda ? encoder transmit polarity inversion bit (1) iren = 0 : 1 = uxtx idle ? 0 ? 0 = uxtx idle ? 1 ? iren = 1 : 1 = uxtx idle ? 1 ? 0 = uxtx idle ? 0 ? bit 12 unimplemented: read as ? 0 ? bit 11 utxbrk: transmit break bit 1 = send sync break on next transmission ? start bit, followed by twelve ? 0 ? bits, followed by stop bit; cleared by hardware upon completion 0 = sync break transmission disabled or completed bit 10 utxen: transmit enable bit (2) 1 = transmit enabled, uxtx pin controlled by uartx 0 = transmit disabled, any pending transmission is aborted and buffer is reset. uxtx pin controlled by port. bit 9 utxbf: transmit buffer full status bit (read-only) 1 = transmit buffer is full 0 = transmit buffer is not full, at least one more character can be written bit 8 trmt: transmit shift register empty bit (read-only) 1 = transmit shift register is empty and transmit buffer is empty (the last transmission has completed) 0 = transmit shift register is not empty, a transmission is in progress or queued note 1: value of bit only affects the transmit properties of the module when the irda encoder is enabled (iren = 1 ). 2: if uarten = 1 , the peripheral inputs and outputs must be configured to an available rpn pin. see section 9.4 ?peripheral pin select? for more information
? 2007 microchip technology inc. preliminary ds39881b-page 159 pic24fj64ga004 family bit 7-6 urxisel1:urxisel0: receive interrupt mode selection bits 11 = interrupt is set on rsr transfer, making the receive buffer full (i.e., has 4 data characters) 10 = interrupt is set on rsr transfer, making the receive buffer 3/4 full (i.e., has 3 data characters) 0x = interrupt is set when any character is received and transferred from the rsr to the receive buffer. receive buffer has one or more characters. bit 5 adden: address character detect bit (bit 8 of received data = 1 ) 1 = address detect mode enabled. if 9-bit mode is not selected, this does not take effect. 0 = address detect mode disabled bit 4 ridle: receiver idle bit (read-only) 1 = receiver is idle 0 = receiver is active bit 3 perr: parity error status bit (read-only) 1 = parity error has been detected for the current character (character at the top of the receive fifo) 0 = parity error has not been detected bit 2 ferr: framing error status bit (read-only) 1 = framing error has been detected for the current character (character at the top of the receive fifo) 0 = framing error has not been detected bit 1 oerr: receive buffer overrun error status bit (read/clear-only) 1 = receive buffer has overflowed 0 = receive buffer has not overflowed (clearing a previously set oerr bit ( 1 0 transition) will reset the receiver buffer and the rsr to the empty state bit 0 urxda: receive buffer data available bit (read-only) 1 = receive buffer has data, at least one more character can be read 0 = receive buffer is empty register 16-2: uxsta: uartx status and control register (continued) note 1: value of bit only affects the transmit properties of the module when the irda encoder is enabled (iren = 1 ). 2: if uarten = 1 , the peripheral inputs and outputs must be configured to an available rpn pin. see section 9.4 ?peripheral pin select? for more information
pic24fj64ga004 family ds39881b-page 160 preliminary ? 2007 microchip technology inc. register 16-3: uxtxreg: uartx transmit register u-x u-x u-x u-x u-x u-x u-x w-x ? ? ? ? ? ? ?utx8 bit 15 bit 8 w-x w-x w-x w-x w-x w-x w-x w-x utx7 utx6 utx5 utx4 utx3 utx2 utx1 utx0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 -9 unimplemented: read as ? 0 ? bit 8 utx8: data of the transmitted character bit (in 9-bit mode) bit 7-0 utx7:utx0: data of the transmitted character bits register 16-4: uxrxreg: uartx receive register u-0 u-0 u-0 u-0 u-0 u-0 u-0 r-0 ? ? ? ? ? ? ? urx8 bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 urx7 urx6 urx5 urx4 urx3 urx2 urx1 urx0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 -9 unimplemented: read as ? 0 ? bit 8 utx8: data of the received character bit (in 9-bit mode) bit 7-0 utx7:utx0: data of the received character bits
? 2007 microchip technology inc. preliminary ds39881b-page 161 pic24fj64ga004 family 17.0 parallel master port (pmp) the parallel master port (pmp) module is a parallel 8-bit i/o module, specifically designed to communicate with a wide variety of parallel devices, such as commu- nication peripherals, lcds, external memory devices and microcontrollers. because the interface to parallel peripherals varies significantly, the pmp is highly configurable. key features of the pmp module include: ? up to 16 programmable address lines ? one chip select line ? programmable strobe options - individual read and write strobes or; - read/write strobe with enable strobe ? address auto-increment/auto-decrement ? programmable address/data multiplexing ? programmable polarity on control signals ? legacy parallel slave port support ? enhanced parallel slave support - address support - 4-byte deep auto-incrementing buffer ? programmable wait states ? selectable input voltage levels figure 17-1: pmp module overview note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the associated ?pic24f family reference manual? chapter. note: a number of the pins for the pmp are not present on pic24fj64ga004 devices. refer to the specific device?s pinout to determine which pins are available. pma<0> pmbe pmrd pmwr pmd<7:0> pmenb pmrd/pmwr pmcs1 pma<1> pma<10:2> pmall pmalh pma<7:0> pma<15:8> eeprom address bus data bus control lines pic24f lcd fifo microcontroller 8-bit data up to 11-bit address parallel master port buffer note 1: devices with 28 pins do not have pma<10:2>. (1)
pic24fj64ga004 family ds39881b-page 162 preliminary ? 2007 microchip technology inc. register 17-1: pmcon: parallel port control register r/w -0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 pmpen ? psidl adrmux1 adrmux0 ptbeen ptwren ptrden bit 15 bit 8 r/w -0 r/w -0 r/w -0 (1) u-0 r/w -0 (1) r/w -0 r/w -0 r/w -0 csf1 csf0 alp ? cs1p bep wrsp rdsp bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 pmpen: parallel master port enable bit 1 = pmp enabled 0 = pmp disabled, no off-chip access performed bit 14 unimplemented: read as ? 0 ? bit 13 psidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-11 adrmux1:adrmux0: address/data multiplexing selection bits (1) 11 = reserved 10 = all 16 bits of address are multiplexed on pmd<7:0> pins 01 = lower 8 bits of address are multiplexed on pmd<7:0> pins, upper 3 bits are multiplexed on pma<10:8> 00 = address and data appear on separate pins bit 10 ptbeen: byte enable port enable bit (16-bit master mode) 1 = pmbe port enabled 0 = pmbe port disabled bit 9 ptwren: write enable strobe port enable bit 1 = pmwr/pmenb port enabled 0 = pmwr/pmenb port disabled bit 8 ptrden: read/write strobe port enable bit 1 = pmrd/pmwr port enabled 0 = pmrd/pmwr port disabled bit 7-6 csf1:csf0: chip select function bits 11 = reserved 10 = pmcs1 functions as chip set 01 = reserved 00 = reserved bit 5 alp: address latch polarity bit (2) 1 = active-high (pmall and pmalh) 0 = active-low (pmall and pmalh ) bit 4 unimplemented: read as ? 0 ? bit 3 cs1p: chip select 1 polarity bit (2) 1 = active-high (pmcs1/pmcs1) 0 =active-low (pmcs1 /pmcs 1 ) note 1: devices with 28 pins do not have pma<10:2>. 2: these bits have no effect when their corresponding pins are used as address lines.
? 2007 microchip technology inc. preliminary ds39881b-page 163 pic24fj64ga004 family bit 2 bep: byte enable polarity bit 1 = byte enable active-high (pmbe) 0 = byte enable active-low (pmbe ) bit 1 wrsp: write strobe polarity bit for slave modes and master mode 2 (pmmode<9:8> = 00,01,10 ): 1 = write strobe active-high (pmwr) 0 = write strobe active-low (pmwr ) for master mode 1 (pmmode<9:8> = 11 ): 1 = enable strobe active-high (pmenb) 0 = enable strobe active-low (pmenb ) bit 0 rdsp: read strobe polarity bit for slave modes and master mode 2 (pmmode<9:8> = 00,01,10 ): 1 = read strobe active-high (pmrd) 0 = read strobe active-low (pmrd ) for master mode 1 (pmmode<9:8> = 11 ): 1 = read/write strobe active-high (pmrd/pmwr ) 0 = read/write strobe active-low (pmrd /pmwr) register 17-1: pmcon: parallel port control register (continued) note 1: devices with 28 pins do not have pma<10:2>. 2: these bits have no effect when their corresponding pins are used as address lines.
pic24fj64ga004 family ds39881b-page 164 preliminary ? 2007 microchip technology inc. register 17-2: pmmode: parallel port mode register r-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 busy irqm1 irqm0 incm1 incm0 mode16 mode1 mode0 bit 15 bit 8 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 waitb1 (1) waitb0 (1) waitm3 waitm2 waitm1 waitm0 waite1 (1) waite0 (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 busy: busy bit (master mode only) 1 = port is busy (not useful when the processor stall is active) 0 = port is not busy bit 14-13 irqm1:irqm0: interrupt request mode bits 11 = interrupt generated when read buffer 3 is read or write buffer 3 is written (buffered psp mode) or on a read or write operation when pma<1:0> = 11 (addressable psp mode only) 10 = no interrupt generated, processor stall activated 01 = interrupt generated at the end of the read/write cycle 00 = no interrupt generated bit 12-11 incm1:incm0: increment mode bits 11 = psp read and write buffers auto-increment (legacy psp mode only) 10 = decrement addr<10:0> by 1 every read/write cycle 01 = increment addr<10:0> by 1 every read/write cycle 00 = no increment or decrement of address bit 10 mode16: 8/16-bit mode bit 1 = 16-bit mode: data register is 16 bits, a read or write to the data register invokes two 8-bit transfers 0 = 8-bit mode: data register is 8 bits, a read or write to the data register invokes one 8-bit transfer bit 9-8 mode1:mode0: parallel port mode select bits 11 = master mode 1 (pmcs1, pmrd/pmwr , pmenb, pmbe, pma and pmd<7:0>) 10 = master mode 2 (pmcs1, pmrd, pmwr, pmbe, pma and pmd<7:0>) 01 = enhanced psp, control signals (pmrd , pmwr , pmcs 1 , pmd<7:0> and pma<1:0>) 00 = legacy parallel slave port, control signals (pmrd , pmwr , pmcs 1 and pmd<7:0>) bit 7-6 waitb1:waitb0: data setup to read/write wait state configuration bits (1) 11 = data wait of 4 t cy ; multiplexed address phase of 4 t cy 10 = data wait of 3 t cy ; multiplexed address phase of 3 t cy 01 = data wait of 2 t cy ; multiplexed address phase of 2 t cy 00 = data wait of 1 t cy ; multiplexed address phase of 1 t cy bit 5-2 waitm3:waitm0: read to byte enable strobe wait state configuration bits 1111 = wait of additional 15 t cy ... 0001 = wait of additional 1 t cy 0000 = no additional wait cycles (operation forced into one t cy ) bit 1-0 waite1:waite0: data hold after strobe wait state configuration bits (1) 11 = wait of 4 t cy 10 = wait of 3 t cy 01 = wait of 2 t cy 00 = wait of 1 t cy note 1: waitb and waite bits are ignored whenever waitm3:waitm0 = 0000 .
? 2007 microchip technology inc. preliminary ds39881b-page 165 pic24fj64ga004 family register 17-3: pmaddr: parallel port address register u-0 r/w -0 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 ?cs1 ? ? ? addr<10:8> (1) bit 15 bit 8 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 addr<7:0> (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14 cs1: chip select 1 bit 1 = chip select 1 is active 0 = chip select 1 is inactive bit 13-11 unimplemented: read as ? 0 ? bit 10-0 addr10:addr0: parallel port destination address bits (1) note 1: devices with 28 pins do not have pma<10:2>. register 17-4: pmaen: parallel port enable register u-0 r/w -0 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 ?pten14 ? ? ?pten10 (1) pten9 (1) pten8 (1) bit 15 bit 8 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 pten7 (1) pten6 (1) pten5 (1) pten4 (1) pten3 (1) pten2 (1) pten1 pten0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14 pten14: pmcs1 strobe enable bit 1 = pmcs1 functions as chip select 0 = pmcs1 pin functions as port i/o bit 13-11 unimplemented: read as ? 0 ? bit 10-2 pten10:pten2: pmp address port enable bits (1) 1 = pma<10:2> function as pmp address lines 0 = pma<10:2> function as port i/o bit 1-0 pten1:pten0: pmalh/pmall strobe enable bits 1 = pma1 and pma0 function as either pma<1:0> or pmalh and pmall 0 = pma1 and pma0 pads functions as port i/o note 1: devices with 28 pins do not have pma<10:2>.
pic24fj64ga004 family ds39881b-page 166 preliminary ? 2007 microchip technology inc. register 17-5: pmstat: parallel port status register r-0 r/w -0, hs u-0 u-0 r-0 r-0 r-0 r-0 ibf ibov ? ? ib3f ib2f ib1f ib0f bit 15 bit 8 r-1 r/w -0, hs u-0 u-0 r-1 r-1 r-1 r-1 obe obuf ? ? ob3e ob2e ob1e ob0e bit 7 bit 0 legend: hs = hardware set bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ibf: input buffer full status bit 1 = all writable input buffer registers are full 0 = some or all of the writable input buffer registers are empty bit 14 ibov: input buffer overflow status bit 1 = a write attempt to a full input byte register occurred (must be cleared in software) 0 = no overflow occurred bit 13-12 unimplemented: read as ? 0 ? bit 11-8 ib3f:ib0f input buffer x status full bits 1 = input buffer contains data that has not been read (reading buffer will clear this bit) 0 = input buffer does not contain any unread data bit 7 obe: output buffer empty status bit 1 = all readable output buffer registers are empty 0 = some or all of the readable output buffer registers are full bit 6 obuf: output buffer underflow status bits 1 = a read occurred from an empty output byte register (must be cleared in software) 0 = no underflow occurred bit 5-4 unimplemented: read as ? 0 ? bit 3-0 ob3e:ob0e output buffer x status empty bit 1 = output buffer is empty (writing data to the buffer will clear this bit) 0 = output buffer contains data that has not been transmitted
? 2007 microchip technology inc. preliminary ds39881b-page 167 pic24fj64ga004 family register 17-6: padcfg1: pad configuration control register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w -0 r/w -0 ? ? ? ? ? ?rtsecsel (1) pmpttl bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-2 unimplemented: read as ? 0 ? bit 1 rtsecsel: rtcc seconds clock output select bit (1) 1 = rtcc seconds clock is selected for the rtcc pin 0 = rtcc alarm pulse is selected for the rtcc pin bit 0 pmpttl: pmp module ttl input buffer select bit 1 = pmp module uses ttl input buffers 0 = pmp module uses schmitt trigger input buffers note 1: to enable the actual rtcc output, the rtcoe (rcfgcal) bit needs to be set.
pic24fj64ga004 family ds39881b-page 168 preliminary ? 2007 microchip technology inc. figure 17-2: legacy parallel slave port example figure 17-3: addressable parallel slave port example table 17-1: slave mode address resolution figure 17-4: master mode, demultiplexed addressing (separate read and write strobes, single chip select) pma<1:0> output register (buffer) input register (buffer) 00 pmdout1<7:0> (0) pmdin1<7:0> (0) 01 pmdout1<15:8> (1) pmdin1<15:8> (1) 10 pmdout2<7:0> (2) pmdin2<7:0> (2) 11 pmdout2<15:8> (3) pmdin2<15:8> (3) pmd<7:0> pmrd pmwr master address bus data bus control lines pmcs 1 pmd<7:0> pmrd pmwr pic24f slave pmcs 1 pmd<7:0> pmrd pmwr master pmcs 1 pma<1:0> address bus data bus control lines pmrd pmwr pic24f slave pmcs 1 pmdout1l (0) pmdout1h (1) pmdout2l (2) pmdout2h (3) pmdin1l (0) pmdin1h (1) pmdin2l (2) pmdin2h (3) pmd<7:0> write address decode read address decode pma<1:0> pmrd pmwr pmd<7:0> pmcs1 pma<10:0> pic24f address bus data bus control lines
? 2007 microchip technology inc. preliminary ds39881b-page 169 pic24fj64ga004 family figure 17-5: master mode, partially multiplexed addressing (separate read and write strobes, single chip select) figure 17-6: master mode, fully multiplexed addressing (separate read and write strobes, single chip select) figure 17-7: example of a multiplexed addressing application figure 17-8: example of a partially multiplexed addressing application pmrd pmwr pmd<7:0> pmcs1 pma<10:8> pmall pma<7:0> pic24f address bus multiplexed data and address bus control lines pmrd pmwr pmd<7:0> pmcs1 pmalh pma<15:8> pic24f multiplexed data and address bus control lines pmall pma<7:0> pmd<7:0> pmalh d<7:0> 373 a<15:0> d<7:0> a<7:0> 373 pmrd pmwr oe wr ce pic24f address bus data bus control lines pmcs 1 pmall a<15:8> pma<10:8> d<7:0> 373 a<10:0> d<7:0> a<7:0> pmrd pmwr oe wr ce pic24f address bus data bus control lines pmcs 1 pmall a<10:8> pmd<7:0>
pic24fj64ga004 family ds39881b-page 170 preliminary ? 2007 microchip technology inc. figure 17-9: example of an 8-bit multiplexed address and data application figure 17-10: parallel eeprom example (up to 11-bit address, 8-bit data) figure 17-11: parallel eeprom example (up to 11-bit address, 16-bit data) figure 17-12: lcd control exam ple (byte mode operation) ale pmrd pmwr rd wr cs pic24f address bus data bus control lines pmcs 1 pmall ad<7:0> parallel peripheral pmd<7:0> pma a d<7:0> pmrd pmwr oe wr ce pic24f address bus data bus control lines pmcs 1 pmd<7:0> parallel eeprom pma a d<7:0> pmrd pmwr oe wr ce pic24f address bus data bus control lines pmcs 1 pmd<7:0> parallel eeprom pmbe a0 pmrd/pmwr d<7:0> pic24f address bus data bus control lines pma0 r/w rs e lcd controller pmcs1 pm<7:0>
? 2007 microchip technology inc. preliminary ds39881b-page 171 pic24fj64ga004 family 18.0 real-time clock and calendar (rtcc) figure 18-1: rtcc block diagram note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the associated ?pic24f family reference manual? chapter. rtcc prescalers rtcc timer comparator compare registers repeat counter year mthday wkdyhr minsec almthdy alwdhr alminsec with masks rtcc interrupt logic rcfgcal alcfgrpt alarm event 32.768 khz input from sosc oscillator 0.5s rtcc clock domain alarm pulse rtcc interrupt cpu clock domain rtcval alrmval rtcc pin rtcoe
pic24fj64ga004 family ds39881b-page 172 preliminary ? 2007 microchip technology inc. 18.1 rtcc module registers the rtcc module registers are organized into three categories: ? rtcc control registers ? rtcc value registers ? alarm value registers 18.1.1 register mapping to limit the register interface, the rtcc timer and alarm time registers are accessed through corre- sponding register pointers. the rtcc value register window (rtcvalh and rtcvall) uses the rtcptr bits (rcfgcal<9:8>) to select the desired timer register pair (see table 18-1). by writing the rtcvalh byte, the rtcc pointer value, rtcptr<1:0> bits, decrement by one until they reach ? 00 ?. once they reach ? 00 ?, the minutes and sec- onds value will be accessible through rtcvalh and rtcvall until the pointer value is manually changed. table 18-1: rtcval register mapping the alarm value register window (alrmvalh and alrmvall) uses the alrmptr bits (alcfgrpt<9:8>) to select the desired alarm register pair (see table 18-2). by writing the alrmvalh byte, the alarm pointer value, alrmptr<1:0> bits, decrement by one until they reach ? 00 ?. once they reach ? 00 ?, the alrmmin and alrmsec value will be accessible through alrmvalh and alrmvall until the pointer value is manually changed. table 18-2: alrmval register mapping considering that the 16-bit core does not distinguish between 8-bit and 16-bit read operations, the user must be aware that when reading either the alrmvalh or alrmvall bytes will decrement the alrmptr<1:0> value. the same applies to the rtcvalh or rtcvall bytes with the rtcptr<1:0> being decremented. 18.1.2 write lock in order to perform a write to any of the rtcc timer registers, the rtcwren bit (rcfgcal<13>) must be set (refer to example 18-1). example 18-1: setting the rtcwren bit rtcptr <1:0> rtcc value register window rtcval<15:8> rtcval<7:0> 00 minutes seconds 01 weekday hours 10 month day 11 ? year alrmptr <1:0> alarm value register window alrmval<15:8> alrmval<7:0> 00 alrmmin alrmsec 01 alrmwd alrmhr 10 alrmmnth alrmday 11 ?? note: this only applies to read operations and not write operations. note: to avoid accidental writes to the timer, it is recommended that the rtcwren bit (rcfgcal<13>) is kept clear at any other time. for the rtcwren bit to be set, there is only 1 instruction cycle time window allowed between the 55h/aa sequence and the setting of rtcwren; therefore, it is recommended that code follow the procedure in example 18-1. mov #nvmkey, w1 ;move the address of nvmkey into w1 mov #0x55, w2 mov #0xaa, w3 mov w2, [w1] ;start 55/aa sequence mov w3, [w1] bset rcfgcal, #13 ;set the rtcwren bit
? 2007 microchip technology inc. preliminary ds39881b-page 173 pic24fj64ga004 family 18.1.3 rtcc control registers register 18-1: rcfgcal: rtcc calibration and configuration register (1) r/w -0 u-0 r/w -0 r-0 r-0 r/w -0 r/w -0 r/w -0 rtcen (2) ? rtcwren rtcsync halfsec (3) rtcoe rtcptr1 rtcptr0 bit 15 bit 8 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 rtcen: rtcc enable bit (2) 1 = rtcc module is enabled 0 = rtcc module is disabled bit 14 unimplemented: read as ? 0 ? bit 13 rtcwren: rtcc value registers write enable bit 1 = rtcvalh and rtcvall registers can be written to by the user 0 = rtcvalh and rtcvall registers are locked out from being written to by the user bit 12 rtcsync: rtcc value registers read synchronization bit 1 = rtcvalh, rtcvall and alcfgrpt registers can change while reading due to a rollover ripple resulting in an invalid data read. if the register is read twice and results in the same data, the data can be assumed to be valid. 0 = rtcvalh, rtcvall or alcfgrpt registers can be read without concern over a rollover ripple bit 11 halfsec: half-second status bit (3) 1 = second half period of a second 0 = first half period of a second bit 10 rtcoe: rtcc output enable bit 1 = rtcc output enabled 0 = rtcc output disabled bit 9-8 rtcptr1:rtcptr0: rtcc value register window pointer bits points to the corresponding rtcc value registers when reading rtcvalh and rtcvall registers; the rtcptr<1:0> value decrements on every read or write of rtcvalh until it reaches ? 00 ?. rtcval<15:8>: 00 = minutes 01 = weekday 10 =month 11 = reserved rtcval<7:0>: 00 = seconds 01 = hours 10 =day 11 =year note 1: the rcfgcal register is only affected by a por. 2: a write to the rtcen bit is only allowed when rtcwren = 1 . 3: this bit is read-only. it is cleared to ? 0 ? on a write to the lower half of the minsec register.
pic24fj64ga004 family ds39881b-page 174 preliminary ? 2007 microchip technology inc. bit 7-0 cal7:cal0: rtc drift calibration bits 01111111 = maximum positive adjustment; adds 508 rtc clock pulses every one minute ... 01111111 = minimum positive adjustment; adds 4 rtc clock pulses every one minute 00000000 = no adjustment 11111111 = minimum negative adjustment; subtracts 4 rtc clock pulses every one minute ... 10000000 = maximum negative adjustment; subtracts 512 rtc clock pulses every one minute register 18-1: rcfgcal: rtcc calibration and configuration register (1) (continued) note 1: the rcfgcal register is only affected by a por. 2: a write to the rtcen bit is only allowed when rtcwren = 1 . 3: this bit is read-only. it is cleared to ? 0 ? on a write to the lower half of the minsec register. register 18-2: padcfg1: pad configuration control register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w -0 r/w -0 ? ? ? ? ? ? rtsecsel (1) pmpttl bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-2 unimplemented: read as ? 0 ? bit 1 rtsecsel: rtcc seconds clock output select bit (1) 1 = rtcc seconds clock is selected for the rtcc pin 0 = rtcc alarm pulse is selected for the rtcc pin bit 0 pmpttl: pmp module ttl input buffer select bit 1 = pmp module uses ttl input buffers 0 = pmp module uses schmitt trigger input buffers note 1: to enable the actual rtcc output, the rtcoe (rcfgcal) bit needs to be set.
? 2007 microchip technology inc. preliminary ds39881b-page 175 pic24fj64ga004 family register 18-3: alcfgrpt: alarm configuration register r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 alrmen chime amask3 amask2 amask1 amask0 alrmptr1 alrmptr0 bit 15 bit 8 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 arpt7 arpt6 arpt5 arpt4 arpt3 arpt2 arpt1 arpt0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 alrmen: alarm enable bit 1 = alarm is enabled (cleared automatically after an alarm event whenever arpt<7:0> = 00h and chime = 0 ) 0 = alarm is disabled bit 14 chime: chime enable bit 1 = chime is enabled; arpt<7:0> bits are allowed to roll over from 00h to ffh 0 = chime is disabled; arpt<7:0> bits stop once they reach 00h bit 13-10 amask3:amask0: alarm mask configuration bits 0000 = every half second 0001 = every second 0010 = every 10 seconds 0011 = every minute 0100 = every 10 minutes 0101 = every hour 0110 = once a day 0111 = once a week 1000 = once a month 1001 = once a year (except when configured for february 29th, once every 4 years) 101x = reserved ? do not use 11xx = reserved ? do not use bit 9-8 alrmptr1:alrmptr0: alarm value register window pointer bits points to the corresponding alarm value registers when reading alrmvalh and alrmvall registers; the alrmptr<1:0> value decrements on every read or write of alrmvalh until it reaches ? 00 ?. alrmval<15:8>: 00 = alrmmin 01 =alrmwd 10 =alrmmnth 11 = unimplemented alrmval<7:0>: 00 = alrmsec 01 =alrmhr 10 =alrmday 11 = unimplemented bit 7-0 arpt7:arpt0: alarm repeat counter value bits 11111111 = alarm will repeat 255 more times ... 00000000 = alarm will not repeat the counter decrements on any alarm event. the counter is prevented from rolling over from 00h to ffh unless chime = 1 .
pic24fj64ga004 family ds39881b-page 176 preliminary ? 2007 microchip technology inc. 18.1.4 rtcval register mappings register 18-4: year: year value register (1) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w -x r/w -x r/w -x r/w -x r/w -x r/w -x r/w -x r/w -x yrten3 yrten2 yrten1 yrten0 yrone3 yrone2 yrone1 yrone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7-4 yrten3:yrten0: binary coded decimal value of year?s tens digit; contains a value from 0 to 9 bit 3-0 yrone3:yrone0: binary coded decimal value of year?s ones digit; contains a value from 0 to 9 note 1: a write to the year register is only allowed when rtcwren = 1 . register 18-5: mthdy: month and day value register (1) u-0 u-0 u-0 r-x r-x r-x r-x r-x ? ? ? mthten0 mthone3 mthone2 mthone1 mthone0 bit 15 bit 8 u-0 u-0 r/w -x r/w -x r/w -x r/w -x r/w -x r/w -x ? ? dayten1 dayten0 dayone3 dayone2 dayone1 dayone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12 mthten0: binary coded decimal value of month?s tens digit; contains a value of 0 or 1 bit 11-8 mthone3:mthone0: binary coded decimal value of month?s ones digit; contains a value from 0 to 9 bit 7-6 unimplemented: read as ? 0 ? bit 5-4 dayten1:dayten0: binary coded decimal value of day?s tens digit; contains a value from 0 to 3 bit 3-0 dayone3:dayone0: binary coded decimal value of day?s ones digit; contains a value from 0 to 9 note 1: a write to this register is only allowed when rtcwren = 1 .
? 2007 microchip technology inc. preliminary ds39881b-page 177 pic24fj64ga004 family register 18-6: wkdyhr: weekday and hours value register (1) u-0 u-0 u-0 u-0 u-0 r/w -x r/w -x r/w -x ? ? ? ? ? wday2 wday1 wday0 bit 15 bit 8 u-0 u-0 r/w -x r/w -x r/w -x r/w -x r/w -x r/w -x ? ? hrten1 hrten0 hrone3 hrone2 hrone1 hrone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 10-8 wday2:wday0: binary coded decimal value of weekday digit; contains a value from 0 to 6 bit 7-6 unimplemented: read as ? 0 ? bit 5-4 hrten1:hrten0: binary coded decimal value of hour?s tens digit; contains a value from 0 to 2 bit 3-0 hrone3:hrone0: binary coded decimal value of hour?s ones digit; contains a value from 0 to 9 note 1: a write to this register is only allowed when rtcwren = 1 . register 18-7: minsec: minutes and seconds value register u-0 r/w -x r/w -x r/w -x r/w -x r/w -x r/w -x r/w -x ? minten2 minten1 minten0 minone3 minone2 minone1 minone0 bit 15 bit 8 u-0 r/w -x r/w -x r/w -x r/w -x r/w -x r/w -x r/w -x ? secten2 secten1 secten0 secone3 secone2 secone1 secone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 minten2:minten0: binary coded decimal value of minute?s tens digit; contains a value from 0 to 5 bit 11-8 minone3:minone0: binary coded decimal value of minute?s ones digit; contains a value from 0 to 9 bit 7 unimplemented: read as ? 0 ? bit 6-4 secten2:secten0: binary coded decimal value of second?s tens digit; contains a value from 0 to 5 bit 3-0 secone3:secone0: binary coded decimal value of second?s ones digit; contains a value from 0 to 9
pic24fj64ga004 family ds39881b-page 178 preliminary ? 2007 microchip technology inc. 18.1.5 alrmval register mappings register 18-8: almthdy: alarm month and day value register (1) u-0 u-0 u-0 r/w -x r/w -x r/w -x r/w -x r/w -x ? ? ? mthten0 mthone3 mthone2 mthone1 mthone0 bit 15 bit 8 u-0 u-0 r/w -x r/w -x r/w -x r/w -x r/w -x r/w -x ? ? dayten1 dayten0 dayone3 dayone2 dayone1 dayone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12 mthten0: binary coded decimal value of month?s tens digit; contains a value of 0 or 1 bit 11-8 mthone3:mthone0: binary coded decimal value of month?s ones digit; contains a value from 0 to 9 bit 7-6 unimplemented: read as ? 0 ? bit 5-4 dayten1:dayten0: binary coded decimal value of day?s tens digit; contains a value from 0 to 3 bit 3-0 dayone3:dayone0: binary coded decimal value of day?s ones digit; contains a value from 0 to 9 note 1: a write to this register is only allowed when rtcwren = 1 . register 18-9: alwdhr: alarm weekday and hours value register (1) u-0 u-0 u-0 u-0 u-0 r/w -x r/w -x r/w -x ? ? ? ? ? wday2 wday1 wday0 bit 15 bit 8 u-0 u-0 r/w -x r/w -x r/w -x r/w -x r/w -x r/w -x ? ? hrten1 hrten0 hrone3 hrone2 hrone1 hrone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 10-8 wday2:wday0: binary coded decimal value of weekday digit; contains a value from 0 to 6 bit 7-6 unimplemented: read as ? 0 ? bit 5-4 hrten1:hrten0: binary coded decimal value of hour?s tens digit; contains a value from 0 to 2 bit 3-0 hrone3:hrone0: binary coded decimal value of hour?s ones digit; contains a value from 0 to 9 note 1: a write to this register is only allowed when rtcwren = 1 .
? 2007 microchip technology inc. preliminary ds39881b-page 179 pic24fj64ga004 family 18.2 calibration the real-time crystal input can be calibrated using the periodic auto-adjust feature. when properly calibrated, the rtcc can provide an error of less than 3 seconds per month. this is accomplished by finding the number of error clock pulses and storing the value into the lower half of the rcfgcal register. the 8-bit signed value loaded into the lower half of rcfgcal is multi- plied by four and will be either added or subtracted from the rtcc timer, once every minute. refer to the steps below for rtcc calibration: 1. using another timer resource on the device, the user must find the error of the 32.768 khz crystal. 2. once the error is known, it must be converted to the number of error clock pulses per minute. equation 18-1: 3. a) if the oscillator is faster then ideal (negative result form step 2), the rcfgcal register value needs to be negative. this causes the specified number of clock pulses to be subtracted from the timer counter once every minute. b) if the oscillator is slower then ideal (positive result from step 2) the rcfgcal register value needs to be positive. this causes the specified number of clock pulses to be subtracted from the timer counter once every minute. 4. divide the number of error clocks per minute by 4 to get the correct cal value and load the rcfgcal register with the correct value. (each 1-bit increment in cal adds or subtracts 4 pulses). writes to the lower half of the rcfgcal register should only occur when the timer is turned off, or immediately after the rising edge of the seconds pulse. register 18-10: alminsec: alarm minutes and seconds value register u-0 r/w -x r/w -x r/w -x r/w -x r/w -x r/w -x r/w -x ? minten2 minten1 minten0 minone3 minone2 minone1 minone0 bit 15 bit 8 u-0 r/w -x r/w -x r/w -x r/w -x r/w -x r/w -x r/w -x ? secten2 secten1 secten0 secone3 secone2 secone1 secone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 minten2:minten0: binary coded decimal value of minute?s tens digit; contains a value from 0 to 5 bit 11-8 minone3:minone0: binary coded decimal value of minute?s ones digit; contains a value from 0 to 9 bit 7 unimplemented: read as ? 0 ? bit 6-4 secten2:secten0: binary coded decimal value of second?s tens digit; contains a value from 0 to 5 bit 3-0 secone3:secone0: binary coded decimal value of second?s ones digit; contains a value from 0 to 9 (ideal frequency ? ? measured frequency) * 60 = clocks per minute ? ideal frequency = 32,768 hz note: it is up to the user to include in the error value the initial error of the crystal, drift due to temperature and drift due to crystal aging.
pic24fj64ga004 family ds39881b-page 180 preliminary ? 2007 microchip technology inc. 18.3 alarm ? configurable from half second to one year ? enabled using the alrmen bit (alcfgrpt<7>, register 18-3) ? one-time alarm and repeat alarm options available 18.3.1 configuring the alarm the alarm feature is enabled using the alrmen bit. this bit is cleared when an alarm is issued. writes to alrmvalh:alrmvall should only take place when alrmen = 0 . as shown in figure 18-2, the interval selection of the alarm is configured through the amask bits (alcfgrpt<13:10>). these bits determine which and how many digits of the alarm must match the clock value for the alarm to occur. the alarm can also be con- figured to repeat based on a preconfigured interval. the amount of times this occurs once the alarm is enabled is stored in the lower half of the alcfgrpt register. when alcfgrpt = 00 and chime bit = 0 (alcfgrpt<14>), the repeat function is disabled and only a single alarm will occur. the alarm can be repeated up to 255 times by loading the lower half of the alcfgrpt register with ffh. after each alarm is issued, the alcfgrpt register is decremented by one. once the register has reached ? 00 ?, the alarm will be issued one last time, after which the alrmen bit will be cleared automatically and the alarm will turn off. indefinite repetition of the alarm can occur if the chime bit = 1 . instead of the alarm being disabled when the alcfgrpt register reaches ? 00 ?, it will roll over to ff and continue counting indefinitely when chime = 1 . 18.3.2 alarm interrupt at every alarm event, an interrupt is generated. in addi- tion, an alarm pulse output is provided that operates at half the frequency of the alarm. this output is completely synchronous to the rtcc clock and can be used as a trigger clock to other peripherals. figure 18-2: alarm mask settings note: changing any of the registers, other then the rcfgcal and alcfgrpt registers and the chime bit while the alarm is enabled (alrmen = 1 ), can result in a false alarm event leading to a false alarm interrupt. to avoid a false alarm event, the timer and alarm values should only be changed while the alarm is disabled (alrmen = 0 ). it is recommended that the alcfgrpt register and chime bit be changed when rtcsync = 0 . note 1: annually, except when configured for february 29. s ss mss mm s s hh mm ss dhhmmss dd hh mm s s mm d d h h mm s s day of the week month day hours minutes seconds alarm mask setting (amask3:amask0) 0000 ? every half second 0001 ? every second 0010 ? every 10 seconds 0011 ? every minute 0100 ? every 10 minutes 0101 ? every hour 0110 ? every day 0111 ? every week 1000 ? every month 1001 ? every year (1)
? 2007 microchip technology inc. preliminary ds39881b-page 181 pic24fj64ga004 family 19.0 programmable cyclic redundancy check (crc) generator the programmable crc generator offers the following features: ? user-programmable polynomial crc equation ? interrupt output ? data fifo 19.1 registers there are four registers used to control programmable crc operation: ? crccon ? crcxor ? crcdat ? crcwdat register 19-1: crccon: crc control register u-0 u-0 r/w -0 r-0 r-0 r-0 r-0 r-0 ? ? csidl vword4 vword3 vword2 vword1 vword0 bit 15 bit 8 r-0 r-1 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 crcful crcmpt ? crcgo plen3 plen2 plen1 plen0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 csidl: crc stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-8 vword4:vword0: pointer value bits indicates the number of valid words in the fifo. has a maximum value of 8 when plen3:plen0 > 7, or 16 when plen3:plen0 7. bit 7 crcful : fifo full bit 1 = fifo is full 0 = fifo is not full bit 6 crcmpt: fifo empty bit 1 = fifo is empty 0 = fifo is not empty bit 5 unimplemented: read as ? 0 ? bit 4 crcgo: start crc bit 1 = start crc serial shifter 0 = crc serial shifter turned off bit 3-0 plen3:plen0: polynomial length bits denotes the length of the polynomial to be generated minus 1.
pic24fj64ga004 family ds39881b-page 182 preliminary ? 2007 microchip technology inc. register 19-2: crcxor: crc xor polynomial register r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 x15 x14 x13 x12 x11 x10 x9 x8 bit 15 bit 8 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 u-0 x7 x6 x5 x4 x3 x2 x1 ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-1 x15:x1: xor of polynomial term x n enable bits bit 0 unimplemented: read as ?0?
? 2007 microchip technology inc. preliminary ds39881b-page 183 pic24fj64ga004 family 19.2 overview the module implements a software configurable crc generator. the terms of the polynomial and its length can be programmed using the crcxor (x<15:1>) bits and the crccon (plen3:plen0) bits, respectively. consider the crc equation: x 16 + x 12 + x 5 + 1 to program this polynomial into the crc generator, the crc register bits should be set as shown in table 19-1. table 19-1: example crc setup note that for the value of x<15:1>, the 12th bit and the 5th bit are set to ? 1 ?, as required by the equation. the 0th bit required by the equation is always xored. for a 16-bit polynomial, the 16th bit is also always assumed to be xored; therefore, the x<15:1> bits do not have the 0th bit or the 16th bit. the topology of a standard crc generator is shown in figure 19-2. figure 19-1: crc shifter details bit name bit value plen3:plen0 1111 x<15:1> 000100000010000 in out bit 0 0 1 p_clk x1 in out bit 1 0 1 p_clk x2 in out bit 2 0 1 p_clk x3 in out bit 15 0 1 p_clk x15 xor d out 01 2 15 plen<3:0> hold hold hold hold crc read bus crc write bus crc shift register
pic24fj64ga004 family ds39881b-page 184 preliminary ? 2007 microchip technology inc. figure 19-2: crc generator reconfigured for x 16 + x 12 + x 5 + 1 19.3 user interface 19.3.1 data interface to start serial shifting, a ? 1 ? must be written to the crcgo bit. the module incorporates a fifo that is 8 deep when plen (plen<3:0>) > 7, and 16 deep, otherwise. the data for which the crc is to be calculated must first be written into the fifo. the smallest data element that can be written into the fifo is one byte. for example, if plen = 5, then the size of the data is plen + 1 = 6. the data must be written as follows: data[5:0] = crc_input[5:0] data[7:6] = ?bxx once data is written into the crcwdat msb (as defined by plen), the value of vword (vword<4:0>) increments by one. the serial shifter starts shifting data into the crc engine when crcgo = 1 and vword > 0. when the msb is shifted out, vword decrements by one. the serial shifter continues shifting until the vword reaches 0. therefore, for a given value of plen, it will take (plen + 1) * vword number of clock cycles to complete the crc calculations. when vword reaches 8 (or 16), the crcful bit will be set. when vword reaches 0, the crcmpt bit will be set. to continually feed data into the crc engine, the rec- ommended mode of operation is to initially ?prime? the fifo with a sufficient number of words so no interrupt is generated before the next word can be written. once that is done, start the crc by setting the crcgo bit to ? 1 ?. from that point onward, the vword bits should be polled. if they read less than 8 or 16, another word can be written into the fifo. to empty words already written into a fifo, the crcgo bit must be set to ? 1 ? and the crc shifter allowed to run until the crcmpt bit is set. also, to get the correct crc reading, it will be necessary to wait for the crcmpt bit to go high before reading the crcwdat register. if a word is written when the crcful bit is set, the vword pointer will roll over to 0. the hardware will then behave as if the fifo is empty. however, the con- dition to generate an interrupt will not be met; therefore, no interrupt will be generated (see section 19.3.2 ?interrupt operation? ). at least one instruction cycle must pass after a write to crcwdat before a read of the vword bits is done. 19.3.2 interrupt operation when the vword4:vword0 bits make a transition from a value of ? 1 ? to ? 0 ?, an interrupt will be generated. 19.4 operation in power save modes 19.4.1 sleep mode if sleep mode is entered while the module is operating, the module will be suspended in its current state until clock execution resumes. 19.4.2 idle mode to continue full module operation in idle mode, the csidl bit must be cleared prior to entry into the mode. if csidl = 1 , the module will behave the same way as it does in sleep mode; pending interrupt events will be passed on, even though the module clocks are not available. d q bit 0 p_clk dq bit 4 p_clk dq bit 5 p_clk dq bit 12 p_clk xor sdox crc read bus crc write bus dq bit 15 p_clk
? 2007 microchip technology inc. preliminary ds39881b-page 185 pic24fj64ga004 family 20.0 10-bit high-speed a/d converter the 10-bit a/d converter has the following key features: ? successive approximation (sar) conversion ? conversion speeds of up to 500 ksps ? up to 13 analog input pins ? external voltage reference input pins ? automatic channel scan mode ? selectable conversion trigger source ? 16-word conversion result buffer ? selectable buffer fill modes ? four result alignment options ? operation during cpu sleep and idle modes depending on the particular device pinout, the 10-bit a/d converter can have up to three analog input pins, designated an0 through an12. in addition, there are two analog input pins for external voltage reference connections. these voltage reference inputs may be shared with other analog input pins. the actual number of analog input pins and external voltage reference input configuration will depend on the specific device. refer to the device data sheet for further details. a block diagram of the a/d converter is shown in figure 20-1. to perform an a/d conversion: 1. configure the a/d module: a) select port pins as analog inputs (ad1pcfg<15:0>). b) select voltage reference source to match expected range on analog inputs (ad1con2<15:13>). c) select the analog conversion clock to match desired data rate with processor clock (ad1con3<7:0>). d) select the appropriate sample/conversion sequence (ad1con1<7:5> and ad1con3<12:8>). e) select how conversion results are presented in the buffer (ad1con1<9:8>). f) select interrupt rate (ad1con2<5:2>). g) turn on a/d module (ad1con1<15>). 2. configure a/d interrupt (if required): a) clear the ad1if bit. b) select a/d interrupt priority. note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the associated ?pic24f family reference manual? chapter.
pic24fj64ga004 family ds39881b-page 186 preliminary ? 2007 microchip technology inc. figure 20-1: 10-bit high-speed a/d converter block diagram (1) comparator 10-bit sar conversion logic v ref + dac an12 an8 an9 an10 an11 an4 an5 an6 an7 an0 an1 an2 an3 v ref - sample control s/h av ss av dd ad1buf0: ad1buff ad1con1 ad1con2 ad1con3 ad1chs0 ad1pcfg ad1cssl control logic data formatting input mux control conversion control pin config. control internal data bus 16 v r + v r - mux a mux b v inh v inl v inh v inh v inl v inl v r + v r - v r select note 1: devices with 28 pins can only use an0-an5 and an9-an12.
? 2007 microchip technology inc. preliminary ds39881b-page 187 pic24fj64ga004 family register 20-1: ad1con1: a/d control register 1 r/w -0 u-0 r/c-0 u-0 u-0 u-0 r/w -0 r/w -0 adon ?adsidl ? ? ?form1form0 bit 15 bit 8 r/w -0 r/w -0 r/w -0 u-0 u-0 r/w -0 r/w -0 hcs r/w -0 hcs ssrc2 ssrc1 ssrc0 ? ? asam samp done bit 7 bit 0 legend: c = clearable bit hcs = hardware cleared, set bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 adon: a/d operating mode bit 1 = a/d converter module is operating 0 = a/d converter is off bit 14 unimplemented: read as ? 0 ? bit 13 adsidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-10 unimplemented: read as ? 0 ? bit 9-8 form1:form0: data output format bits 11 = signed fractional ( sddd dddd dd00 0000 ) 10 = fractional ( dddd dddd dd00 0000 ) 01 = signed integer ( ssss sssd dddd dddd ) 00 = integer ( 0000 00dd dddd dddd ) bit 7-5 ssrc2:ssrc0: conversion trigger source select bits 111 = internal counter ends sampling and starts conversion (auto-convert) 110 = reserved 10x = reserved 011 = reserved 010 = timer3 compare ends sampling and starts conversion 001 = active transition on int0 pin ends sampling and starts conversion 000 = clearing samp bit ends sampling and starts conversion bit 4-3 unimplemented: read as ? 0 ? bit 2 asam: a/d sample auto-start bit 1 = sampling begins immediately after last conversion completes. samp bit is auto-set. 0 = sampling begins when samp bit is set bit 1 samp: a/d sample enable bit 1 = a/d sample/hold amplifier is sampling input 0 = a/d sample/hold amplifier is holding bit 0 done: a/d conversion status bit 1 = a/d conversion is done 0 = a/d conversion is not done
pic24fj64ga004 family ds39881b-page 188 preliminary ? 2007 microchip technology inc. register 20-2: ad1con2: a/d control register 2 r/w -0 r/w -0 r/w -0 r/w -0 u-0 r/w -0 u-0 u-0 vcfg2 vcfg1 vcfg0 ? ? cscna ? ? bit 15 bit 8 r-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 bufs ? smpi3 smpi2 smpi1 smpi0 bufm alts bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 vcfg2:vcfg0: voltage reference configuration bits bit 12-11 unimplemented: read as ? 0 ? bit 10 cscna: scan input selections for ch0+ s/h input for mux a input multiplexer setting bit 1 = scan inputs 0 = do not scan inputs bit 9-8 unimplemented: read as ? 0 ? bit 7 bufs: buffer fill status bit (valid only when bufm = 1 ) 1 = a/d is currently filling buffer 08-0f, user should access data in 00-07 0 = a/d is currently filling buffer 00-07, user should access data in 08-0f bit 6 unimplemented: read as ? 0 ? bit 5-2 smpi3:smpi0: sample/convert sequences per interrupt selection bits 1111 = interrupts at the completion of conversion for each 16th sample/convert sequence 1110 = interrupts at the completion of conversion for each 15th sample/convert sequence ..... 0001 = interrupts at the completion of conversion for each 2nd sample/convert sequence 0000 = interrupts at the completion of conversion for each sample/convert sequence bit 1 bufm: buffer mode select bit 1 = buffer configured as two 8-word buffers (ad1bufn<15:8> and ad1bufn<7:0>) 0 = buffer configured as one 16-word buffer (ad1bufn<15:0>) bit 0 alts: alternate input sample mode select bit 1 = uses mux a input multiplexer settings for first sample, then alternates between mux b and mux a input multiplexer settings for all subsequent samples 0 = always uses mux a input multiplexer settings vcfg2:vcfg0 v r +v r - 000 av dd av ss 001 external v ref + pin av ss 010 av dd external v ref - pin 011 external v ref + pin external v ref - pin 1xx av dd av ss
? 2007 microchip technology inc. preliminary ds39881b-page 189 pic24fj64ga004 family register 20-3: ad1con3: a/d control register 3 r/w -0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 adrc ? ? samc4 samc3 samc2 samc1 samc0 bit 15 bit 8 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 adcs7 adcs6 adcs5 adcs4 adcs3 adcs2 adcs1 adcs0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 adrc: a/d conversion clock source bit 1 = a/d internal rc clock 0 = clock derived from system clock bit 14-13 unimplemented: read as ? 0 ? bit 12-8 samc4:samc0: auto-sample time bits 11111 = 31 t ad 00001 = 1 t ad 00000 = 0 t ad (not recommended) bit 7-0 adcs7:adcs0: a/d conversion clock select bits 11111111 = 128 ? t cy 00000001 = t cy 00000000 = t cy /2
pic24fj64ga004 family ds39881b-page 190 preliminary ? 2007 microchip technology inc. register 20-4: ad1chs0: a/d input select register r/w -0 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 ch0nb ? ? ? ch0sb3 (1) ch0sb2 (1) ch0sb1 (1) ch0sb0 (1) bit 15 bit 8 r/w -0 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 ch0na ? ? ? ch0sa3 (1) ch0sa2 (1) ch0sa1 (1) ch0sa0 (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ch0nb: channel 0 negative input select for mux b multiplexer setting bit 1 = channel 0 negative input is an1 0 = channel 0 negative input is v r - bit 14-12 unimplemented: read as ? 0 ? bit 11-8 ch0sb3:ch0sb0: channel 0 positive input select for mux b multiplexer setting bits (1) 1100 = channel 0 positive input is an12 1011 = channel 0 positive input is an11 0001 = channel 0 positive input is an1 0000 = channel 0 positive input is an0 bit 7 ch0na: channel 0 negative input select for mux a multiplexer setting bit 1 = channel 0 negative input is an1 0 = channel 0 negative input is v r - bit 6-4 unimplemented: read as ? 0 ? bit 3-0 ch0sa3:ch0sa0: channel 0 positive input select for mux a multiplexer setting bits (1) 1100 = channel 0 positive input is an12 1011 = channel 0 positive input is an11 0001 = channel 0 positive input is an1 0000 = channel 0 positive input is an0 note 1: devices with 28 pins can use only an0-an5 and an9-an12.
? 2007 microchip technology inc. preliminary ds39881b-page 191 pic24fj64ga004 family register 20-5: ad1pcfg: a/d po rt configuration register u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ? pcfg12 pcfg11 pcfg10 pcfg9 pcfg8 bit 15 bit 8 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 pcfg7 pcfg6 pcfg5 pcfg4 pcfg3 pcfg2 pcfg1 pcfg0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-0 pcfg12:pcfg0: analog input pin configuration control bits (1) 1 = pin for corresponding analog channel is configured in digital mode; i/o port read enabled 0 = pin configured in analog mode; i/o port read disabled, a/d samples pin voltage note 1: devices with 28 pins can use only pcfg0-pcfg5 and pcfg9-pcfg12. register 20-6: ad1cssl: a/d input scan select register u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 ? ? ? cssl12 cssl11 cssl10 cssl9 cssl8 bit 15 bit 8 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 cssl7 cssl6 cssl5 cssl4 cssl3 cssl2 cssl1 cssl0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-0 cssl12:cssl0: a/d input pin scan selection bits (1) 1 = corresponding analog channel selected for input scan 0 = analog channel omitted from input scan note 1: devices with 28 pins can use only cssl0-cssl5 and cssl9-cssl12.
pic24fj64ga004 family ds39881b-page 192 preliminary ? 2007 microchip technology inc. equation 20-1: a/d conversion clock period (1) figure 20-2: 10-bit a/d converter analog input model t ad = t cy (adcs + 1) adcs = 2 t ad t cy ? 1 note 1: based on t cy = t cy /2; doze mode and pll are disabled. 2 c pin va rs anx v t = 0.6v v t = 0.6v i leakage r ic 250 sampling switch r ss c hold = dac capacitance v ss v dd = 4.4 pf (typical) 500 na legend: c pin v t i leakage r ic r ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch resistance = sample/hold capacitance (from dac) various junctions note: c pin value depends on device package and is not tested. effect of c pin negligible if rs 5 k . r ss 5 k (typical) 6-11 pf (typical)
? 2007 microchip technology inc. preliminary ds39881b-page 193 pic24fj64ga004 family figure 20-3: a/d transfer function 10 0000 0001 (513) 10 0000 0010 (514) 10 0000 0011 (515) 01 1111 1101 (509) 01 1111 1110 (510) 01 1111 1111 (511) 11 1111 1110 (1022) 11 1111 1111 (1023) 00 0000 0000 (0) 00 0000 0001 (1) output code 10 0000 0000 (512) (v inh ? v inl ) v r - v r + ? v r - 1024 512*(v r + ? v r -) 1024 v r + v r - + v r - + 1023*(v r + ? v r -) 1024 v r - + 0 (binary (decimal)) voltage level
pic24fj64ga004 family ds39881b-page 194 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds39881b-page 195 pic24fj64ga004 family 21.0 comparator module figure 21-1: comparator i/o operating modes note 1: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the associated ?pic24f family reference manual? chapter. 2: this peripheral contains output functions that may need to be configured by the peripheral pin select feature. for more information, see section 9.4 ?peripheral pin select? . c2 c2in- v in - v in + c2in+ cv ref c2in+ c2out (1) cmcon<7> c1 c1in- v in - v in + c1in+ cv ref c1in+ c1out (1) cmcon<6> c1neg c1pos c2neg c2pos c1inv c2inv c1outen c2outen c1en c2en note 1: this peripheral?s outputs must be assigned to an available rpn pin before use. please see section 9.4 ?peripheral pin select? for more information.
pic24fj64ga004 family ds39881b-page 196 preliminary ? 2007 microchip technology inc. register 21-1: cmcon: comparator control register r/w -0 u-0 r/c-0 r/c-0 r/w -0 r/w -0 r/w -0 r/w -0 cmidl ? c2evt c1evt c2en c1en c2outen (1) c1outen (2) bit 15 bit 8 r-0 r-0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 c2out c1out c2inv c1inv c2neg c2pos c1neg c1pos bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 cmidl: stop in idle mode 1 = when device enters idle mode, module does not generate interrupts. module is still enabled. 0 = continue normal module operation in idle mode bit 14 unimplemented: read as ? 0 ? bit 13 c2evt: comparator 2 event 1 = comparator output changed states 0 = comparator output did not change states bit 12 c1evt: comparator 1 event 1 = comparator output changed states 0 = comparator output did not change states bit 11 c2en: comparator 2 enable 1 = comparator is enabled 0 = comparator is disabled bit 10 c1en: comparator 1 enable 1 = comparator is enabled 0 = comparator is disabled bit 9 c2outen: comparator 2 output enable (1) 1 = comparator output is driven on the output pad 0 = comparator output is not driven on the output pad bit 8 c1outen: comparator 1 output enable (2) 1 = comparator output is driven on the output pad 0 = comparator output is not driven on the output pad bit 7 c2out: comparator 2 output bit when c2inv = 0 : 1 =c2 v in + > c2 v in - 0 =c2 v in + < c2 v in - when c2inv = 1 : 0 =c2 v in + > c2 v in - 1 =c2 v in + < c2 v in - bit 6 c1out: comparator 1 output bit when c1inv = 0 : 1 =c1 v in + > c1 v in - 0 =c1 v in + < c1 v in - when c1inv = 1 : 0 =c1 v in + > c1 v in - 1 =c1 v in + < c1 v in -
? 2007 microchip technology inc. preliminary ds39881b-page 197 pic24fj64ga004 family bit 5 c2inv: comparator 2 output inversion bit 1 = c2 output inverted 0 = c2 output not inverted bit 4 c1inv: comparator 1 output inversion bit 1 = c1 output inverted 0 = c1 output not inverted bit 3 c2neg: comparator 2 negative input configure bit 1 = input is connected to v in + 0 = input is connected to v in - see figure 21-1 for the comparator modes. bit 2 c2pos: comparator 2 positive input configure bit 1 = input is connected to v in + 0 = input is connected to cv ref see figure 21-1 for the comparator modes. bit 1 c1neg: comparator 1 negative input configure bit 1 = input is connected to v in + 0 = input is connected to v in - see figure 21-1 for the comparator modes. bit 0 c1pos: comparator 1 positive input configure bit 1 = input is connected to v in + 0 = input is connected to cv ref see figure 21-1 for the comparator modes. note 1: if c2outen = 1 , the c2out peripheral output must be configured to an available rpx pin. see section 9.4 ?peripheral pin select? for more information. 2: if c1outen = 1 , the c1out peripheral output must be configured to an available rpx pin. see section 9.4 ?peripheral pin select? for more information. register 21-1: cmcon: comparator control register (continued)
pic24fj64ga004 family ds39881b-page 198 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds39881b-page 199 pic24fj64ga004 family 22.0 comparator voltage reference 22.1 configuring the comparator voltage reference the voltage reference module is controlled through the cvrcon register (register 22-1). the comparator voltage reference provides two ranges of output voltage, each with 16 distinct levels. the range to be used is selected by the cvrr bit (cvrcon<5>). the primary difference between the ranges is the size of the steps selected by the cv ref selection bits (cvr3:cvr0), with one range offering finer resolution. the comparator reference supply voltage can come from either v dd and v ss , or the external v ref + and v ref -. the voltage source is selected by the cvrss bit (cvrcon<4>). the settling time of the comparator voltage reference must be considered when changing the cv ref output. figure 22-1: comparator voltage reference block diagram note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the associated ?pic24f family reference manual? chapter. 16-to-1 mux cvr3:cvr0 8r r cvren cvrss = 0 av dd v ref + cvrss = 1 8r cvrss = 0 v ref - cvrss = 1 r r r r r r 16 steps cvrr cv ref av ss
pic24fj64ga004 family ds39881b-page 200 preliminary ? 2007 microchip technology inc. register 22-1: cvrcon: comparator voltage reference control register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 cvren cvroe cvrr cvrss cvr3 cvr2 cvr1 cvr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 cvren: comparator voltage reference enable bit 1 =cv ref circuit powered on 0 =cv ref circuit powered down bit 6 cvroe: comparator v ref output enable bit 1 =cv ref voltage level is output on cv ref pin 0 =cv ref voltage level is disconnected from cv ref pin bit 5 cvrr: comparator v ref range selection bit 1 =cv rsrc range should be 0 to 0.625 cv rsrc with cv rsrc /24 step size 0 =cv rsrc range should be 0.25 to 0.719 cv rsrc with cv rsrc /32 step size bit 4 cvrss: comparator v ref source selection bit 1 = comparator reference source cv rsrc = v ref + ? v ref - 0 = comparator reference source cv rsrc = av dd ? av ss bit 3-0 cvr3:cvr0: comparator v ref value selection 0 cvr3:cvr0 15 bits when cvrr = 1 : cv ref = (cvr<3:0>/ 24) ? (cv rsrc ) when cvrr = 0 : cv ref = 1/4 ? (cv rsrc ) + (cvr<3:0>/32) ? (cv rsrc )
? 2007 microchip technology inc. preliminary ds39881b-page 201 pic24fj64ga004 family 23.0 special features pic24fj64ga family devices include several features intended to maximize application flexibility and reli- ability, and minimize cost through elimination of external components. these are: ? flexible configuration ? watchdog timer (wdt) ? code protection ? jtag boundary scan interface ? in-circuit serial programming ? in-circuit emulation 23.1 configuration bits the configuration bits can be programmed (read as ? 0 ?), or left unprogrammed (read as ? 1 ?), to select various device configurations. these bits are mapped starting at program memory location f80000h. a complete list is shown in table 23-1. a detailed explanation of the vari- ous bit functions is provided in register 23-1 through register 23-4. note that address f80000h is beyond the user program memory space. in fact, it belongs to the configuration memory space (800000h-ffffffh) which can only be accessed using table reads and table writes. 23.1.1 considerations for configuring pic24fj64ga004 family devices in pic24fj64ga004 family devices, the configuration bytes are implemented as volatile memory. this means that configuration data must be programmed each time the device is powered up. configuration data is stored in the two words at the top of the on-chip program memory space, known as the flash configuration words. their specific locations are shown in table 23-1. these are packed representations of the actual device configuration bits, whose actual locations are distributed among five locations in config- uration space. the configuration data is automatically loaded from the flash configuration words to the proper configuration registers during device resets. table 23-1: flash configuration word locations for pic24fj64ga004 family devices when creating applications for these devices, users should always specifically allocate the location of the flash configuration word for configuration data. this is to make certain that program code is not stored in this address when the code is compiled. the configuration bits are reloaded from the flash configuration word on any device reset. the upper byte of both flash configuration words in program memory should always be ? 1111 1111 ?. this makes them appear to be nop instructions in the remote event that their locations are ever executed by accident. since configuration bits are not implemented in the corresponding locations, writing ? 1 ?s to these locations has no effect on device operation. note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the associated ?pic24f family reference manual? chapter. note: configuration data is reloaded on all types of device resets. device configuration word addresses 12 pic24fj16ga 002bfeh 002bfch pic24fj32ga 0057feh 0057fch pic24fj48ga 0083feh 0083fch pic24fj64ga 00abfeh 00abfch
pic24fj64ga004 family ds39881b-page 202 preliminary ? 2007 microchip technology inc. register 23-1: cw1: flash configuration word 1 u-1 u-1 u-1 u-1 u-1 u-1 u-1 u-1 ? ? ? ? ? ? ? ? bit 23 bit 16 r-0 r/po-1 r/po-1 r/po-1 r/po-1 u-1 r/po-1 r/po-1 ? jtagen gcp gwrp debug ? ics1 ics0 bit 15 bit 8 r/po-1 r/po-1 u-1 r/po-1 r/po-1 r/po-1 r/po-1 r/po-1 fwdten windis ? fwpsa wdtps3 wdtps2 wdtps1 wdtps0 bit 7 bit 0 legend: r = reserved r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 23-16 unimplemented: read as ? 1 ? bit 15 reserved: maintain as ? 1 ? bit 14 jtagen: jtag port enable bit 1 = jtag port is enabled 0 = jtag port is disabled bit 13 gcp: general segment program memory code protection bit 1 = code protection is disabled 0 = code protection is enabled for the entire program memory space bit 12 gwrp: general segment code flash write protection bit 1 = writes to program memory are allowed 0 = writes to program memory are disabled bit 11 debug : background debugger enable bit 1 = device resets into operational mode 0 = device resets into debug mode bit 10 reserved bit 9-8 ics1:ics0: emulator pin placement select bits 11 = emulator emuc/emud pins are shared with pgc1/pgd1 10 = emulator emuc/emud pins are shared with pgc2/pgd2 01 = emulator emuc/emud pins are shared with pgc3/pgd3 00 = reserved; do not use bit 7 fwdten: watchdog timer enable bit 1 = watchdog timer is enabled 0 = watchdog timer is disabled bit 6 windis: windowed watchdog timer disable bit 1 = standard watchdog timer enabled 0 = windowed watchdog timer enabled; fwdten must be ? 1 ? bit 5 unimplemented: read as ? 1 ? bit 4 fwpsa: wdt prescaler ratio select bit 1 = prescaler ratio of 1:128 0 = prescaler ratio of 1:32
? 2007 microchip technology inc. preliminary ds39881b-page 203 pic24fj64ga004 family bit 3-0 wdtps3:wdtps0: watchdog timer postscaler select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 register 23-1: cw1: flash configuration word 1 (continued)
pic24fj64ga004 family ds39881b-page 204 preliminary ? 2007 microchip technology inc. register 23-2: cw2: flash configuration word 2 u-1 u-1 u-1 u-1 u-1 u-1 u-1 u-1 ? ? ? ? ? ? ? ? bit 23 bit 16 r/po-1 u-1 u-1 u-1 u-1 r/po-1 u-1 r/po-1 ieso ? ? ? ? fnosc2 fnosc1 fnosc0 bit 15 bit 8 r/po-1 r/po-1 r/po-1 r/po-1 u-1 r/po-1 r/po-1 r/po-1 fcksm1 fcksm0 osciofcn iol1way ? i2c1sel poscmd1 poscmd0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 23-16 unimplemented: read as ? 1 ? bit 15 ieso: internal external switchover bit 1 = ieso mode (two-speed start-up) enabled 0 = ieso mode (two-speed start-up) disabled bit 14-11 unimplemented: read as ? 1 ? bit 10-8 fnosc2:fnosc0: initial oscillator select bits 111 = fast rc oscillator with postscaler (frcdiv) 110 = reserved 101 = low-power rc oscillator (lprc) 100 = secondary oscillator (sosc) 011 = primary oscillator with p ll module (xtpll, hspll, ecpll) 010 = primary oscillator (xt, hs, ec) 001 = fast rc oscillator with postscaler and pll module (frcpll) 000 = fast rc oscillator (frc) bit 7-6 fcksm1:fcksm0: clock switching and fail-safe clock monitor configuration bits 1x = clock switching and fail-safe clock monitor are disabled 01 = clock switching is enabled, fail-safe clock monitor is disabled 00 = clock switching is enabled, fail-safe clock monitor is enabled bit 5 osciofcn: osco pin configuration bit if poscmd1:poscmd0 = 11 or 00 : 1 = osco/clko/ra3 functions as clko (f osc /2) 0 = osco/clko/ra3 functions as port i/o (ra3) if poscmd1:poscmd0 = 10 or 01 : osciofcn has no effect on osco/clko/ra3. bit 4 iol1way: iolock one-way set enable bit 1 = the osccon bit can be set once, provided the unlock sequence has been completed. once set, the peripheral pin select registers cannot be written to a second time. 0 = the osccon bit can be set and cleared as needed, provided the unlock sequence has been completed. bit 4-3 unimplemented: read as ? 1 ? bit 2 i2c1sel: i2c1 pin select bit 1 = use default scl1/sda1 pins 0 = use alternate scl1/sda1 pins bit 1-0 poscmd1:poscmd0: primary oscillator configuration bits 11 = primary oscillator disabled 10 = hs oscillator mode selected 01 = xt oscillator mode selected 00 = ec oscillator mode selected
? 2007 microchip technology inc. preliminary ds39881b-page 205 pic24fj64ga004 family register 23-3: devid: device id register uuuuuuuu ? ? ? ? ? ? ? ? bit 23 bit 16 uurrrrrr ? ? famid7 famid6 famid5 famid4 famid3 famid2 bit 15 bit 8 rrrrrrrr famid1 famid0 dev5 dev4 dev3 dev2 dev1 dev0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 23-14 unimplemented: read as ? 1 ? bit 13-6 famid7:famid0: device family identifier bits 00010001 = pic24fj64ga004 family bit 5-0 dev5:dev0: individual device identifier bits 000100 = pic24fj16ga002 000101 = pic24fj32ga002 000110 = pic24fj48ga002 000111 = pic24fj64ga002 001100 = pic24fj16ga004 001101 = pic24fj32ga004 001110 = pic24fj48ga004 001111 = pic24fj64ga004
pic24fj64ga004 family ds39881b-page 206 preliminary ? 2007 microchip technology inc. register 23-4: devrev: device revision register uuuuuuuu ? ? ? ? ? ? ? ? bit 23 bit 16 uuuuuuur ? ? ? ? ? ? ?majrv2 bit 15 bit 8 rruuurrr majrv1 majrv0 ? ? ? dot2 dot1 dot0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 23-9 unimplemented: read as ? 0 ? bit 8-6 majrv2:majrv0: major revision identifier bits bit 5-3 unimplemented: read as ? 0 ? bit 2-0 dot2:dot0: minor revision identifier bits
? 2007 microchip technology inc. preliminary ds39881b-page 207 pic24fj64ga004 family 23.2 on-chip voltage regulator all of the pic24fj64ga004 family of devices power their core digital logic at a nominal 2.5v. this may create an issue for designs that are required to operate at a higher typical voltage, such as 3.3v. to simplify system design, all devices in the pic24fj64ga family incorporate an on-chip regulator that allows the device to run its core logic from v dd . the regulator is controlled by the disvreg pin. tying v ss to the pin enables the regulator, which in turn, pro- vides power to the core from the other v dd pins. when the regulator is enabled, a low-esr capacitor (such as ceramic) must be connected to the v ddcore /v cap pin (figure 23-1). this helps to maintain the stability of the regulator. the recommended value for the filter capacitor is provided in section 26.1 ?dc characteristics? . if disvreg is tied to v dd , the regulator is disabled. in this case, separate power for the core logic at a nomi- nal 2.5v must be supplied to the device on the v ddcore /v cap pin to run the i/o pins at higher voltage levels, typically 3.3v. alternatively, the v ddcore /v cap and v dd pins can be tied together to operate at a lower nominal voltage. refer to figure 23-1 for possible configurations. 23.2.1 voltage regulator tracking mode and low-voltage detection when it is enabled, the on-chip regulator provides a constant voltage of 2.5v nominal to the digital core logic. the regulator can provide this level from a v dd of about 2.5v, all the way up to the device?s v ddmax . it does not have the capability to boost v dd levels below 2.5v. in order to prevent ?brown out? conditions when the volt- age drops too low for the regulator, the regulator enters tracking mode. in tracking mode, the regulator output follows v dd , with a typical voltage drop of 100 mv. when the device enters tracking mode, it is no longer possible to operate at full speed. to provide information about when the device enters tracking mode, the on-chip regulator includes a simple, low-voltage detect circuit. when v dd drops below full-speed oper- ating voltage, the circuit sets the low-voltage detect interrupt flag, lvdif (pir3<6>). this can be used to generate an interrupt and put the application into a low-power operational mode, or trigger an orderly shutdown. low-voltage detection is only available when the regulator is enabled. figure 23-1: connections for the on-chip regulator 23.2.2 on-chip regulator and por when the voltage regulator is enabled, it takes approxi- mately 20 s for it to generate output. during this time, designated as t startup , code execution is disabled. t startup is applied every time the device resumes operation after any power-down, including sleep mode. if the regulator is disabled, a separate power-up timer (pwrt) is automatically enabled. the pwrt adds a fixed delay of 64 ms nominal delay at device start-up. v dd disvreg v ddcore /v cap v ss pic24fj64ga 3.3v (1) 2.5v (1) regulator disabled (disvreg tied to v dd ): v dd disvreg v ddcore /v cap v ss pic24fj64ga 2.5v (1) regulator disabled (v dd tied to v ddcore ): v dd disvreg v ddcore /v cap v ss pic24fj64ga c efc 3.3v (10 f typ) regulator enabled (disvreg tied to v ss ): note 1: these are typical operating voltages. refer to section 26.1 ?dc characteristics? for the full operating ranges of v dd and v ddcore .
pic24fj64ga004 family ds39881b-page 208 preliminary ? 2007 microchip technology inc. 23.2.3 on-chip regulator and bor when the on-chip regulator is enabled, pic24fj64ga family devices also have a simple brown-out capability. if the voltage supplied to the regulator is inadequate to maintain the tracking level, the regulator reset circuitry will generate a brown-out reset. this event is captured by the bor flag bit (rcon<1>). the brown-out voltage levels are specified in section 26.1 ?dc characteristics? . 23.2.4 power-up requirements the on-chip regulator is designed to meet the power-up requirements for the device. if the application does not use the regulator, then strict power-up conditions must be adhered to. while powering up, v ddcore must never exceed v dd by 0.3 volts. 23.2.5 voltage regulator standby mode when enabled, the on-chip regulator always consumes a small incremental amount of current over i dd /i pd , including when the device is in sleep mode, even though the core digital logic does not require power. to provide additional savings in applications where power resources are critical, the regulator automatically disables itself whenever the device goes into sleep mode. this feature is controlled by the vregs bit (rcon<8>). by default, this bit is cleared, which enables standby mode. when waking up from standby mode, the regulator will require around 190 s to wake-up. this extra time is needed to ensure that the regulator can source enough current to power the flash memory. for applications which require a faster wake-up time, it is possible to disable regulator standby mode. the vregs bit (rcon<8>) can be set to turn off standby mode so that the flash stays powered when in sleep mode and the device can wake-up in 10 s. when vregs is set, the power consumption while in sleep mode, will be approximately 40 a higher than power consumption when the regulator is allowed to enter standby mode. 23.3 watchdog timer (wdt) for pic24fj64ga004 family devices, the wdt is driven by the lprc oscillator. when the wdt is enabled, the clock source is also enabled. the nominal wdt clock source from lprc is 31 khz. this feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. the prescaler is set by the fwpsa configuration bit. with a 31 khz input, the prescaler yields a nominal wdt time-out period (t wdt ) of 1 ms in 5-bit mode, or 4 ms in 7-bit mode. a variable postscaler divides down the wdt prescaler output and allows for a wide range of time-out periods. the postscaler is controlled by the wdtps3:wdtps0 configuration bits (flash configuration word 1<3:0>), which allow the selection of a total of 16 settings, from 1:1 to 1:32,768. using the prescaler and postscaler, time-out periods ranging from 1 ms to 131 seconds can be achieved. the wdt, prescaler and postscaler are reset: ? on any device reset ? on the completion of a clock switch, whether invoked by software (i.e., setting the oswen bit after changing the nosc bits), or by hardware (i.e., fail-safe clock monitor) ? when a pwrsav instruction is executed (i.e., sleep or idle mode is entered) ? when the device exits sleep or idle mode to resume normal operation ?by a clrwdt instruction during normal execution if the wdt is enabled, it will continue to run during sleep or idle modes. when the wdt time-out occurs, the device will wake the device and code execution will continue from where the pwrsav instruction was exe- cuted. the corresponding sleep or idle bits (rcon<3:2>) will need to be cleared in software after the device wakes up. the wdt flag bit, wdto (rcon<4>), is not auto- matically cleared following a wdt time-out. to detect subsequent wdt events, the flag must be cleared in software. note: for more information, see section 26.0 ?electrical characteristics? . note: the clrwdt and pwrsav instructions clear the prescaler and postscaler counts when executed.
? 2007 microchip technology inc. preliminary ds39881b-page 209 pic24fj64ga004 family figure 23-2: wdt block diagram 23.3.1 control register the wdt is enabled or disabled by the fwdten device configuration bit. when the fwdten configuration bit is set, the wdt is always enabled. the wdt can be optionally controlled in software when the fwdten configuration bit has been programmed to ? 0 ?. the wdt is enabled in software by setting the swdten control bit (rcon<5>). the swdten control bit is cleared on any device reset. the software wdt option allows the user to enable the wdt for critical code segments and disable the wdt during non-critical segments for maximum power savings. 23.4 jtag interface pic24fj64ga004 family devices implement a jtag interface, which supports boundary scan device testing as well as in-circuit programming. 23.5 program verification and code protection for all devices in the pic24fj64ga004 family of devices, the on-chip program memory space is treated as a single block. code protection for this block is controlled by one configuration bit, gcp. this bit inhibits external reads and writes to the program memory space. it has no direct effect in normal execution mode. write protection is controlled by the gwrp bit in the configuration word. when gwrp is programmed to ? 0 ?, internal write and erase operations to program memory are blocked. 23.5.1 configuration register protection the configuration registers are protected against inadvertent or unwanted changes or reads in two ways. the primary protection method is the same as that of the rp registers ? shadow registers contain a compli- mentary value which is constantly compared with the actual value. to safeguard against unpredictable events, configura- tion bit changes resulting from individual cell level disruptions (such as esd events) will cause a parity error and trigger a device reset. the data for the configuration registers is derived from the flash configuration words in program memory. when the gcp bit is set, the source data for device configuration is also protected as a consequence. lprc input wdt overflow wake from sleep 31 khz prescaler postscaler fwpsa swdten fwdten reset all device resets sleep or idle mode lprc control clrwdt instr. pwrsav instr. (5-bit/7-bit) 1:1 to 1:32.768 wdtps3:wdtps0 1 ms/4 ms exit sleep or idle mode wdt counter transition to new clock source
pic24fj64ga004 family ds39881b-page 210 preliminary ? 2007 microchip technology inc. 23.6 in-circuit serial programming pic24fj64ga004 family microcontrollers can be seri- ally programmed while in the end application circuit. this is simply done with two lines for clock (pgcx) and data (pgdx) and three other lines for power, ground and the programming voltage. this allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. 23.7 in-circuit debugger when mplab ? icd 2 is selected as a debugger, the in-circuit debugging functionality is enabled. this func- tion allows simple debugging functions when used with mplab ide. debugging functionality is controlled through the emucx (emulation/debug clock) and emudx (emulation/debug data) pins. to use the in-circuit debugger function of the device, the design must implement icsp connections to mclr , v dd , v ss , pgcx, pgdx and the emudx/emucx pin pair. in addition, when the feature is enabled, some of the resources are not available for general use. these resources include the first 80 bytes of data ram and two i/o pins.
? 2007 microchip technology inc. preliminary ds39881b-page 211 pic24fj64ga004 family 24.0 development support the pic ? microcontrollers are supported with a full range of hardware and software development tools: ? integrated development environment - mplab ? ide software ? assemblers/compilers/linkers - mpasm tm assembler - mplab c18 and mplab c30 c compilers -mplink tm object linker/ mplib tm object librarian - mplab asm30 assembler/linker/library ? simulators - mplab sim software simulator ?emulators - mplab ice 2000 in-circuit emulator - mplab real ice? in-circuit emulator ? in-circuit debugger - mplab icd 2 ? device programmers - picstart ? plus development programmer - mplab pm3 device programmer - pickit? 2 development programmer ? low-cost demonstration and development boards and evaluation kits 24.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. the mplab ide is a windows ? operating system-based application that contains: ? a single graphical interface to all debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor with color-coded context ? a multiple project manager ? customizable data windows with direct edit of contents ? high-level source code debugging ? visual device initializer for easy register initialization ? mouse over variable inspection ? drag and drop variables from source to watch windows ? extensive on-line help ? integration of select third party tools, such as hi-tech software c compilers and iar c compilers the mplab ide allows you to: ? edit your source files (either assembly or c) ? one touch assemble (or compile) and download to pic mcu emulator and simulator tools (automatically updates all project information) ? debug using: - source files (assembly or c) - mixed assembly and c - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increased flexibility and power.
pic24fj64ga004 family ds39881b-page 212 preliminary ? 2007 microchip technology inc. 24.2 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for all pic mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: ? integration into mplab ide projects ? user-defined macros to streamline assembly code ? conditional assembly for multi-purpose source files ? directives that allow complete control over the assembly process 24.3 mplab c18 and mplab c30 c compilers the mplab c18 and mplab c30 code development systems are complete ansi c compilers for microchip?s pic18 and pic24 families of microcontrol- lers and the dspic30 and dspic33 family of digital sig- nal controllers. these compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 24.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c18 c compiler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 24.5 mplab asm30 assembler, linker and librarian mplab asm30 assembler produces relocatable machine code from symbolic assembly language for dspic30f devices. mplab c30 c compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: ? support for the entire dspic30f instruction set ? support for fixed-point and floating-point data ? command line interface ? rich directive set ? flexible macro language ? mplab ide compatibility 24.6 mplab sim software simulator the mplab sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic ? dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab sim software simulator fully supports symbolic debugging using the mplab c18 and mplab c30 c compilers, and the mpasm and mplab asm30 assemblers. the software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool.
? 2007 microchip technology inc. preliminary ds39881b-page 213 pic24fj64ga004 family 24.7 mplab ice 2000 high-performance in-circuit emulator the mplab ice 2000 in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for pic microcontrollers. software control of the mplab ice 2000 in-circuit emulator is advanced by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator system with enhanced trace, trigger and data monitor- ing features. interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. the architecture of the mplab ice 2000 in-circuit emulator allows expansion to support new pic microcontrollers. the mplab ice 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft ? windows ? 32-bit operating system were chosen to best make these features available in a simple, unified application. 24.8 mplab real ice in-circuit emulator system mplab real ice in-circuit emulator system is microchip?s next generation high-speed emulator for microchip flash dsc ? and mcu devices. it debugs and programs pic ? and dspic ? flash microcontrollers with the easy-to-use, powerful graphical user interface of the mplab integrated development environment (ide), included with each kit. the mplab real ice probe is connected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with the popular mplab icd 2 system (rj11) or with the new high speed, noise tolerant, low- voltage differential signal (lvds) interconnection (cat5). mplab real ice is field upgradeable through future firmware downloads in mplab ide. in upcoming releases of mplab ide, new devices will be supported, and new features will be added, such as software break- points and assembly code trace. mplab real ice offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 24.9 mplab icd 2 in-circuit debugger microchip?s in-circuit debugger, mplab icd 2, is a powerful, low-cost, run-time development tool, connecting to the host pc via an rs-232 or high-speed usb interface. this tool is based on the flash pic mcus and can be used to develop for these and other pic mcus and dspic dscs. the mplab icd 2 utilizes the in-circuit debugging capability built into the flash devices. this feature, along with microchip?s in-circuit serial programming tm (icsp tm ) protocol, offers cost- effective, in-circuit flash debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by setting breakpoints, single step- ping and watching variables, and cpu status and peripheral registers. running at full speed enables testing hardware and applications in real time. mplab icd 2 also serves as a development programmer for selected pic devices. 24.10 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various package types. the icsp? cable assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc connection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an sd/mmc card for file storage and secure data applications.
pic24fj64ga004 family ds39881b-page 214 preliminary ? 2007 microchip technology inc. 24.11 picstart plus development programmer the picstart plus development programmer is an easy-to-use, low-cost, prototype programmer. it connects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer supports most pic devices in dip packages up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant. 24.12 pickit 2 development programmer the pickit? 2 development programmer is a low-cost programmer and selected flash device debugger with an easy-to-use interface for programming many of microchip?s baseline, mid-range and pic18f families of flash memory microcontrollers. the pickit 2 starter kit includes a prototyping development board, twelve sequential lessons, software and hi-tech?s picc? lite c compiler, and is designed to help get up to speed quickly using pic ? microcontrollers. the kit provides everything needed to program, evaluate and develop applications using microchip?s powerful, mid-range flash memory family of microcontrollers. 24.13 demonstration, development and evaluation boards a wide variety of demonstration, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully func- tional systems. most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, switches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demon- stration/development board series of circuits, microchip has a line of evaluation kits and demonstration software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart ? battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. check the microchip web page (www.microchip.com) and the latest ?product selector guide? (ds00148) for the complete list of demonstration, development and evaluation kits.
? 2007 microchip technology inc. preliminary ds39881b-page 215 pic24fj64ga004 family 25.0 instruction set summary the pic24f instruction set adds many enhancements to the previous pic ? mcu instruction sets, while main- taining an easy migration from previous pic mcu instruction sets. most instructions are a single program memory word. only three instructions require two program memory locations. each single-word instruction is a 24-bit word divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. the instruction set is highly orthogonal and is grouped into four basic categories: ? word or byte-oriented operations ? bit-oriented operations ? literal operations ? control operations table 25-1 shows the general symbols used in describing the instructions. the pic24f instruction set summary in table 25-2 lists all the instructions, along with the status flags affected by each instruction. most word or byte-oriented w register instructions (including barrel shift instructions) have three operands: ? the first source operand which is typically a register ?wb? without any address modifier ? the second source operand which is typically a register ?ws? with or without an address modifier ? the destination of the result which is typically a register ?wd? with or without an address modifier however, word or byte-oriented file register instructions have two operands: ? the file register specified by the value ?f? ? the destination, which could either be the file register ?f? or the w0 register, which is denoted as ?wreg? most bit-oriented instructions (including simple rotate/shift instructions) have two operands: ? the w register (with or without an address modifier) or file register (specified by the value of ?ws? or ?f?) ? the bit in the w register or file register (specified by a literal value or indirectly by the contents of register ?wb?) the literal instructions that involve data movement may use some of the following operands: ? a literal value to be loaded into a w register or file register (specified by the value of ?k?) ? the w register or file register where the literal value is to be loaded (specified by ?wb? or ?f?) however, literal instructions that involve arithmetic or logical operations use some of the following operands: ? the first source operand which is a register ?wb? without any address modifier ? the second source operand which is a literal value ? the destination of the result (only if not the same as the first source operand) which is typically a register ?wd? with or without an address modifier the control instructions may use some of the following operands: ? a program memory address ? the mode of the table read and table write instructions all instructions are a single word, except for certain double-word instructions, which were made dou- ble-word instructions so that all the required informa- tion is available in these 48 bits. in the second word, the 8msbs are ? 0 ?s. if this second word is executed as an instruction (by itself), it will execute as a nop . most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruc- tion. in these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a nop . notable exceptions are the bra (uncondi- tional/computed branch), indirect call/goto , all table reads and writes, and return/retfie instructions, which are single-word instructions but take two or three cycles. certain instructions that involve skipping over the sub- sequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. moreover, double-word moves require two cycles. the double-word instructions execute in two instruction cycles. note: this chapter is a brief summary of the pic24f instruction set architecture, and is not intended to be a comprehensive refer- ence source.
pic24fj64ga004 family ds39881b-page 216 preliminary ? 2007 microchip technology inc. table 25-1: symbols used in opcode descriptions field description #text means literal defined by ? text ? (text) means ?content of text ? [text] means ?the location addressed by text ? { } optional field or operation register bit field .b byte mode selection .d double-word mode selection .s shadow register select .w word mode selection (default) bit4 4-bit bit selection field (used in word addressed instructions) {0...15} c, dc, n, ov, z mcu status bits: carry, digit carry, negative, overflow, sticky zero expr absolute address, label or expression (resolved by the linker) f file register address {0000h...1fffh} lit1 1-bit unsigned literal {0,1} lit4 4-bit unsigned literal {0...15} lit5 5-bit unsigned literal {0...31} lit8 8-bit unsigned literal {0...255} lit10 10-bit unsigned literal {0...255} for byte mode, {0:1023} for word mode lit14 14-bit unsigned literal {0...16384} lit16 16-bit unsigned literal {0...65535} lit23 23-bit unsigned literal {0...8388608}; lsb must be ? 0 ? none field does not require an entry, may be blank pc program counter slit10 10-bit signed literal {-512...511} slit16 16-bit signed literal {-32768...32767} slit6 6-bit signed literal {-16...16} wb base w register {w0..w15} wd destination w register { wd, [wd], [wd++], [wd--], [++wd], [--wd] } wdo destination w register { wnd, [wnd], [wnd++], [wnd--], [++wnd], [--wnd], [wnd+wb] } wm,wn dividend, divisor working r egister pair (direct addressing) wn one of 16 working registers {w0..w15} wnd one of 16 destination working registers {w0..w15} wns one of 16 source working registers {w0..w15} wreg w0 (working register used in file register instructions) ws source w register { ws, [ws], [ws++], [ws--], [++ws], [--ws] } wso source w register { wns, [wns], [wns++], [wns--], [++wns], [--wns], [wns+wb] }
? 2007 microchip technology inc. preliminary ds39881b-page 217 pic24fj64ga004 family table 25-2: instruction set overview assembly mnemonic assembly syntax description # of words # of cycles status flags affected add add f f = f + wreg 1 1 c, dc, n, ov, z add f,wreg wreg = f + wreg 1 1 c, dc, n, ov, z add #lit10,wn wd = lit10 + wd 1 1 c, dc, n, ov, z add wb,ws,wd wd = wb + ws 1 1 c, dc, n, ov, z add wb,#lit5,wd wd = wb + lit5 1 1 c, dc, n, ov, z addc addc f f = f + wreg + (c) 1 1 c, dc, n, ov, z addc f,wreg wreg = f + wreg + (c) 1 1 c, dc, n, ov, z addc #lit10,wn wd = lit10 + wd + (c) 1 1 c, dc, n, ov, z addc wb,ws,wd wd = wb + ws + (c) 1 1 c, dc, n, ov, z addc wb,#lit5,wd wd = wb + lit5 + (c) 1 1 c, dc, n, ov, z and and f f = f .and. wreg 1 1 n, z and f,wreg wreg = f .and. wreg 1 1 n, z and #lit10,wn wd = lit10 .and. wd 1 1 n, z and wb,ws,wd wd = wb .and. ws 1 1 n, z and wb,#lit5,wd wd = wb .and. lit5 1 1 n, z asr asr f f = arithmetic right shift f 1 1 c, n, ov, z asr f,wreg wreg = arithmetic right shift f 1 1 c, n, ov, z asr ws,wd wd = arithmetic right shift ws 1 1 c, n, ov, z asr wb,wns,wnd wnd = arithmetic right shift wb by wns 1 1 n, z asr wb,#lit5,wnd wnd = arithmetic right shift wb by lit5 1 1 n, z bclr bclr f,#bit4 bit clear f 1 1 none bclr ws,#bit4 bit clear ws 1 1 none bra bra c,expr branch if carry 1 1 (2) none bra ge,expr branch if greater than or equal 1 1 (2) none bra geu,expr branch if unsigned greater than or equal 1 1 (2) none bra gt,expr branch if greater than 1 1 (2) none bra gtu,expr branch if unsigned greater than 1 1 (2) none bra le,expr branch if less than or equal 1 1 (2) none bra leu,expr branch if unsigned less than or equal 1 1 (2) none bra lt,expr branch if less than 1 1 (2) none bra ltu,expr branch if unsigned less than 1 1 (2) none bra n,expr branch if negative 1 1 (2) none bra nc,expr branch if not carry 1 1 (2) none bra nn,expr branch if not negative 1 1 (2) none bra nov,expr branch if not overflow 1 1 (2) none bra nz,expr branch if not zero 1 1 (2) none bra ov,expr branch if overflow 1 1 (2) none bra expr branch unconditionally 1 2 none bra z,expr branch if zero 1 1 (2) none bra wn computed branch 1 2 none bset bset f,#bit4 bit set f 1 1 none bset ws,#bit4 bit set ws 1 1 none bsw bsw.c ws,wb write c bit to ws 1 1 none bsw.z ws,wb write z bit to ws 1 1 none btg btg f,#bit4 bit toggle f 1 1 none btg ws,#bit4 bit toggle ws 1 1 none btsc btsc f,#bit4 bit test f, skip if clear 1 1 (2 or 3) none btsc ws,#bit4 bit test ws, skip if clear 1 1 (2 or 3) none
pic24fj64ga004 family ds39881b-page 218 preliminary ? 2007 microchip technology inc. btss btss f,#bit4 bit test f, skip if set 1 1 (2 or 3) none btss ws,#bit4 bit test ws, skip if set 1 1 (2 or 3) none btst btst f,#bit4 bit test f 1 1 z btst.c ws,#bit4 bit test ws to c 1 1 c btst.z ws,#bit4 bit test ws to z 1 1 z btst.c ws,wb bit test ws to c 1 1 c btst.z ws,wb bit test ws to z 1 1 z btsts btsts f,#bit4 bit test then set f 1 1 z btsts.c ws,#bit4 bit test ws to c, then set 1 1 c btsts.z ws,#bit4 bit test ws to z, then set 1 1 z call call lit23 call subroutine 2 2 none call wn call indirect subroutine 1 2 none clr clr f f = 0x0000 1 1 none clr wreg wreg = 0x0000 1 1 none clr ws ws = 0x0000 1 1 none clrwdt clrwdt clear watchdog timer 1 1 wdto, sleep com com f f = f 11n, z com f,wreg wreg = f 11n, z com ws,wd wd = ws 11n, z cp cp f compare f with wreg 1 1 c, dc, n, ov, z cp wb,#lit5 compare wb with lit5 1 1 c, dc, n, ov, z cp wb,ws compare wb with ws (wb ? ws) 1 1 c, dc, n, ov, z cp0 cp0 f compare f with 0x0000 1 1 c, dc, n, ov, z cp0 ws compare ws with 0x0000 1 1 c, dc, n, ov, z cp1 cp1 f compare f with 0xffff 1 1 c, dc, n, ov, z cp1 ws compare ws with 0xffff 1 1 c, dc, n, ov, z cpb cpb f compare f with wreg, with borrow 1 1 c, dc, n, ov, z cpb wb,#lit5 compare wb with lit5, with borrow 1 1 c, dc, n, ov, z cpb wb,ws compare wb with ws, with borrow (wb ? ws ? c ) 1 1 c, dc, n, ov, z cpseq cpseq wb,wn compare wb with wn, skip if = 1 1 (2 or 3) none cpsgt cpsgt wb,wn compare wb with wn, skip if > 1 1 (2 or 3) none cpslt cpslt wb,wn compare wb with wn, skip if < 1 1 (2 or 3) none cpsne cpsne wb,wn compare wb with wn, skip if 11 (2 or 3) none daw daw wn wn = decimal adjust wn 1 1 c dec dec f f = f ?1 1 1 c, dc, n, ov, z dec f,wreg wreg = f ?1 1 1 c, dc, n, ov, z dec ws,wd wd = ws ? 1 1 1 c, dc, n, ov, z dec2 dec2 f f = f ? 2 1 1 c, dc, n, ov, z dec2 f,wreg wreg = f ? 2 1 1 c, dc, n, ov, z dec2 ws,wd wd = ws ? 2 1 1 c, dc, n, ov, z disi disi #lit14 disable interrupts for k instruction cycles 1 1 none div div.sw wm,wn signed 16/16-bit integer divide 1 18 n, z, c, ov div.sd wm,wn signed 32/16-bit integer divide 1 18 n, z, c, ov div.uw wm,wn unsigned 16/16-bit integer divide 1 18 n, z, c, ov div.ud wm,wn unsigned 32/16-bit integer divide 1 18 n, z, c, ov exch exch wns,wnd swap wns with wnd 1 1 none table 25-2: instruction set overview (continued) assembly mnemonic assembly syntax description # of words # of cycles status flags affected
? 2007 microchip technology inc. preliminary ds39881b-page 219 pic24fj64ga004 family ff1l ff1l ws,wnd find first one from left (msb) side 1 1 c ff1r ff1r ws,wnd find first one from right (lsb) side 1 1 c goto goto expr go to address 2 2 none goto wn go to indirect 1 2 none inc inc f f = f + 1 1 1 c, dc, n, ov, z inc f,wreg wreg = f + 1 1 1 c, dc, n, ov, z inc ws,wd wd = ws + 1 1 1 c, dc, n, ov, z inc2 inc2 f f = f + 2 1 1 c, dc, n, ov, z inc2 f,wreg wreg = f + 2 1 1 c, dc, n, ov, z inc2 ws,wd wd = ws + 2 1 1 c, dc, n, ov, z ior ior f f = f .ior. wreg 1 1 n, z ior f,wreg wreg = f .ior. wreg 1 1 n, z ior #lit10,wn wd = lit10 .ior. wd 1 1 n, z ior wb,ws,wd wd = wb .ior. ws 1 1 n, z ior wb,#lit5,wd wd = wb .ior. lit5 1 1 n, z lnk lnk #lit14 link frame pointer 1 1 none lsr lsr f f = logical right shift f 1 1 c, n, ov, z lsr f,wreg wreg = logical right shift f 1 1 c, n, ov, z lsr ws,wd wd = logical right shift ws 1 1 c, n, ov, z lsr wb,wns,wnd wnd = logical right shift wb by wns 1 1 n, z lsr wb,#lit5,wnd wnd = logical right shift wb by lit5 1 1 n, z mov mov f,wn move f to wn 1 1 none mov [wns+slit10],wnd move [wns+slit10] to wnd 1 1 none mov f move f to f 1 1 n, z mov f,wreg move f to wreg 1 1 n, z mov #lit16,wn move 16-bit literal to wn 1 1 none mov.b #lit8,wn move 8-bit literal to wn 1 1 none mov wn,f move wn to f 1 1 none mov wns,[wns+slit10] move wns to [wns+slit10] 1 1 mov wso,wdo move ws to wd 1 1 none mov wreg,f move wreg to f 1 1 n, z mov.d wns,wd move double from w(ns):w(ns+1) to wd 1 2 none mov.d ws,wnd move double from ws to w(nd+1):w(nd) 1 2 none mul mul.ss wb,ws,wnd {wnd+1, wnd} = signed(wb) * signed(ws) 1 1 none mul.su wb,ws,wnd {wnd+1, wnd} = signed(wb) * unsigned(ws) 1 1 none mul.us wb,ws,wnd {wnd+1, wnd} = unsigned(wb) * signed(ws) 1 1 none mul.uu wb,ws,wnd {wnd+1, wnd} = unsigned(wb) * unsigned(ws) 1 1 none mul.su wb,#lit5,wnd {wnd+1, wnd} = signed(wb) * unsigned(lit5) 1 1 none mul.uu wb,#lit5,wnd {wnd+1, wnd} = unsigned(wb) * unsigned(lit5) 1 1 none mul f w3:w2 = f * wreg 1 1 none neg neg f f = f + 1 1 1 c, dc, n, ov, z neg f,wreg wreg = f + 1 1 1 c, dc, n, ov, z neg ws,wd wd = ws + 1 1 1 c, dc, n, ov, z nop nop no operation 1 1 none nopr no operation 1 1 none pop pop f pop f from top-of-stack (tos) 1 1 none pop wdo pop from top-of-stack (tos) to wdo 1 1 none pop.d wnd pop from top-of-stack (tos) to w(nd):w(nd+1) 1 2 none pop.s pop shadow registers 1 1 all table 25-2: instruction set overview (continued) assembly mnemonic assembly syntax description # of words # of cycles status flags affected
pic24fj64ga004 family ds39881b-page 220 preliminary ? 2007 microchip technology inc. push push f push f to top-of-stack (tos) 1 1 none push wso push wso to top-of-stack (tos) 1 1 none push.d wns push w(ns):w(ns+1) to top-of-stack (tos) 1 2 none push.s push shadow registers 1 1 none pwrsav pwrsav #lit1 go into sleep or idle mode 1 1 wdto, sleep rcall rcall expr relative call 1 2 none rcall wn computed call 1 2 none repeat repeat #lit14 repeat next instruction lit14 + 1 times 1 1 none repeat wn repeat next instruction (wn) + 1 times 1 1 none reset reset software device reset 1 1 none retfie retfie return from interrupt 1 3 (2) none retlw retlw #lit10,wn return with literal in wn 1 3 (2) none return return return from subroutine 1 3 (2) none rlc rlc f f = rotate left through carry f 1 1 c, n, z rlc f,wreg wreg = rotate left through carry f 1 1 c, n, z rlc ws,wd wd = rotate left through carry ws 1 1 c, n, z rlnc rlnc f f = rotate left (no carry) f 1 1 n, z rlnc f,wreg wreg = rotate left (no carry) f 1 1 n, z rlnc ws,wd wd = rotate left (no carry) ws 1 1 n, z rrc rrc f f = rotate right through carry f 1 1 c, n, z rrc f,wreg wreg = rotate right through carry f 1 1 c, n, z rrc ws,wd wd = rotate right through carry ws 1 1 c, n, z rrnc rrnc f f = rotate right (no carry) f 1 1 n, z rrnc f,wreg wreg = rotate right (no carry) f 1 1 n, z rrnc ws,wd wd = rotate right (no carry) ws 1 1 n, z se se ws,wnd wnd = sign-extended ws 1 1 c, n, z setm setm f f = ffffh 1 1 none setm wreg wreg = ffffh 1 1 none setm ws ws = ffffh 1 1 none sl sl f f = left shift f 1 1 c, n, ov, z sl f,wreg wreg = left shift f 1 1 c, n, ov, z sl ws,wd wd = left shift ws 1 1 c, n, ov, z sl wb,wns,wnd wnd = left shift wb by wns 1 1 n, z sl wb,#lit5,wnd wnd = left shift wb by lit5 1 1 n, z sub sub f f = f ? wreg 1 1 c, dc, n, ov, z sub f,wreg wreg = f ? wreg 1 1 c, dc, n, ov, z sub #lit10,wn wn = wn ? lit10 1 1 c, dc, n, ov, z sub wb,ws,wd wd = wb ? ws 1 1 c, dc, n, ov, z sub wb,#lit5,wd wd = wb ? lit5 1 1 c, dc, n, ov, z subb subb f f = f ? wreg ? (c ) 1 1 c, dc, n, ov, z subb f,wreg wreg = f ? wreg ? (c ) 1 1 c, dc, n, ov, z subb #lit10,wn wn = wn ? lit10 ? (c ) 1 1 c, dc, n, ov, z subb wb,ws,wd wd = wb ? ws ? (c ) 1 1 c, dc, n, ov, z subb wb,#lit5,wd wd = wb ? lit5 ? (c ) 1 1 c, dc, n, ov, z subr subr f f = wreg ? f 1 1 c, dc, n, ov, z subr f,wreg wreg = wreg ? f 1 1 c, dc, n, ov, z subr wb,ws,wd wd = ws ? wb 1 1 c, dc, n, ov, z subr wb,#lit5,wd wd = lit5 ? wb 1 1 c, dc, n, ov, z table 25-2: instruction set overview (continued) assembly mnemonic assembly syntax description # of words # of cycles status flags affected
? 2007 microchip technology inc. preliminary ds39881b-page 221 pic24fj64ga004 family subbr subbr f f = wreg ? f ? (c ) 1 1 c, dc, n, ov, z subbr f,wreg wreg = wreg ? f ? (c ) 1 1 c, dc, n, ov, z subbr wb,ws,wd wd = ws ? wb ? (c ) 1 1 c, dc, n, ov, z subbr wb,#lit5,wd wd = lit5 ? wb ? (c ) 1 1 c, dc, n, ov, z swap swap.b wn wn = nibble swap wn 1 1 none swap wn wn = byte swap wn 1 1 none tblrdh tblrdh ws,wd read prog<23:16> to wd<7:0> 1 2 none tblrdl tblrdl ws,wd read prog<15:0> to wd 1 2 none tblwth tblwth ws,wd write ws<7:0> to prog<23:16> 1 2 none tblwtl tblwtl ws,wd write ws to prog<15:0> 1 2 none ulnk ulnk unlink frame pointer 1 1 none xor xor f f = f .xor. wreg 1 1 n, z xor f,wreg wreg = f .xor. wreg 1 1 n, z xor #lit10,wn wd = lit10 .xor. wd 1 1 n, z xor wb,ws,wd wd = wb .xor. ws 1 1 n, z xor wb,#lit5,wd wd = wb .xor. lit5 1 1 n, z ze ze ws,wnd wnd = zero-extend ws 1 1 c, z, n table 25-2: instruction set overview (continued) assembly mnemonic assembly syntax description # of words # of cycles status flags affected
pic24fj64ga004 family ds39881b-page 222 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds39881b-page 223 pic24fj64ga004 family 26.0 electrical characteristics this section provides an overview of the pic24fj64ga family electrical characteristics. additional information will be provided in future revisions of this document as it becomes available. absolute maximum ratings for the pic24fj64ga family are listed below. exposure to these maximum rating conditions for extended periods may affect device reliability. functional operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this specification, is not implied. absolute maximum ratings (?) ambient temperature under bias................................................................................................. ............-40c to +100c storage temperature ............................................................................................................ .................. -65c to +150c voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +4.0v voltage on any combined analog and digital pin and mclr , with respect to v ss ......................... -0.3v to (v dd + 0.3v) voltage on any digital only pin with respect to v ss .................................................................................. -0.3v to +6.0v voltage on v ddcore with respect to v ss ................................................................................................. -0.3v to +3.0v maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin (note 1) ................................................................................................................250 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by all ports .............................................................................................. .........................200 ma maximum current sourced by all ports (note 1) ....................................................................................................200 ma note 1: maximum allowable current is a function of device maximum power dissipation (see table 26-1). ?notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic24fj64ga004 family ds39881b-page 224 preliminary ? 2007 microchip technology inc. 26.1 dc characteristics figure 26-1: pic24fj64ga004 family voltage-frequency graph (industrial) table 26-1: thermal operating conditions rating symbol min typ max unit pic24fj64ga family: operating junction temperature range t j -40 ? +125 c operating ambient temperature range t a -40 ? +85 c power dissipation: internal chip power dissipation: p int = v dd x (i dd ? i oh ) p d p int + p i / o w i/o pin power dissipation: p i / o = ({v dd ? v oh } x i oh ) + (v ol x i ol ) maximum allowed power dissipation p dmax (t j ? t a )/ ja w frequency voltage (v ddcore ) (1) 3.00v 2.00v 32 mhz 2.75v 2.50v 2.25v 2.75v 16 mhz 2.25v for frequencies between 16 mhz and 32 mhz, f max = (64 mhz/v) * (v ddcore ? 2v) + 16 mhz. note 1: w hen the voltage regulator is disabled, v dd and v ddcore must be maintained so that v ddcore v dd 3.6v. pic24fj64ga004/32ga004/64ga002/32ga002 table 26-2: thermal packaging characteristics characteristic symbol typ max unit notes package thermal resistance, 300 mil soic ja 49 ? c/w (note 1) package thermal resistance, 6x6x0.9 mm qfn ja 33.7 ? c/w (note 1) package thermal resistance, 8x8x1 mm qfn ja 28 ? c/w (note 1) package thermal resistance, 10x10x1 mm tqfp ja 39.3 ? c/w (note 1) note 1: junction to ambient thermal resistance, theta- ja ( ja ) numbers are achieved by package simulations.
? 2007 microchip technology inc. preliminary ds39881b-page 225 pic24fj64ga004 family table 26-3: dc characteristics: temperature and voltage specifications dc characteristics standard operating conditions: 2.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. symbol characteristic min typ (1) max units conditions operating voltage dc10 supply voltage v dd 2.2 ? 3.6 v regulator enabled v dd v ddcore ? 3.6 v regulator disabled v ddcore 2.0 ? 2.75 v regulator disabled dc12 v dr ram data retention voltage (2) 1.5 ? ? v dc16 v por v dd start voltage to ensure internal power-on reset signal ?v ss ?v dc17 s vdd v dd rise rate to ensure internal power-on reset signal 0.5 ? ? v/ms 0-3.3v in 0.1s 0-2.5v in 60 ms note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: this is the limit to which v dd can be lowered without losing ram data.
pic24fj64ga004 family ds39881b-page 226 preliminary ? 2007 microchip technology inc. table 26-4: dc characteristics: operating current (i dd ) dc characteristics standard operating conditions: 2.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial parameter no. typical (1) max units conditions operating current (i dd ): pmd bits are set (2) dc20 .650 .850 ma -40c 2.0v (3) 1 mips dc20a .650 .850 ma +25c dc20b .650 .850 ma +85c dc20d 1.2 1.6 ma -40c 3.3v (4) dc20e 1.2 1.6 ma +25c dc20f 1.2 1.6 ma +85c dc23 2.6 3.4 ma -40c 2.0v (3) 4 mips dc23a 2.6 3.4 ma +25c dc23b 2.6 3.4 ma +85c dc23d 4.1 5.4 ma -40c 3.3v (4) dc23e 4.1 5.4 ma +25c dc23f 4.1 5.4 ma +85c dc24 13.5 17.6 ma -40c 2.5v (3) 16 mips dc24a 13.5 17.6 ma +25c dc24b 13.5 17.6 ma +85c dc24d 15 20 ma -40c 3.3v (4) dc24e 15 20 ma +25c dc24f 15 20 ma +85c dc31 13 17 a -40c 2.0v (3) lprc (31 khz) dc31a 13 17 a+25c dc31b 20 26 a+85c dc31d 54 70 a -40c 3.3v (4) dc31e 54 70 a+25c dc31f 95 124 a+85c note 1: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements are as follows: osci driven with external square wave from rail to rail. all i/o pins are configured as inputs and pulled to v dd . m clr = v dd ; wdt and fscm are disabled. cpu, sram, program memory and data memory are operational. no peripheral modules are operating and all of the peripheral module disable (pmd) bits are set. 3: on-chip voltage regulator disabled (disvreg tied to v dd ). 4: on-chip voltage regulator enabled (disvreg tied to v ss ).
? 2007 microchip technology inc. preliminary ds39881b-page 227 pic24fj64ga004 family table 26-5: dc characteristics: idle current (i idle ) dc characteristics standard operating conditions: 2.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial parameter no. typical (1) max units conditions idle current (i idle ): core off, clock on base current, pmd bits are set (2) dc40 150 200 a-40c 2.0v (3) 1 mips dc40a 150 200 a+25c dc40b 150 200 a+85c dc40d 250 325 a-40c 3.3v (4) dc40e 250 325 a+25c dc40f 250 325 a+85c dc43 .55 .72 ma -40c 2.0v (3) 4 mips dc43a .55 .72 ma +25c dc43b .55 .72 ma +85c dc43d .82 1.1 ma -40c 3.3v (4) dc43e .82 1.1 ma +25c dc43f .82 1.1 ma +85c dc47 3 4 ma -40c 2.5v (3) 16 mips dc47a 3 4 ma +25c dc47b 3 4 ma +85c dc47c 3.5 4.6 ma -40c 3.3v (4) dc47d 3.5 4.6 ma +25c dc47e 3.5 4.6 ma +85c dc50 .85 1.1 ma -40c 2.0v (3) frc (4 mips) dc50a .85 1.1 ma +25c dc50b .85 1.1 ma +85c dc50d 1.2 1.6 ma -40c 3.3v (4) dc50e 1.2 1.6 ma +25c dc50f 1.2 1.6 ma +85c dc51 4 6 a-40c 2.0v (3) lprc (31 khz) dc51a 4 6 a+25c dc51b 7 9 a+85c dc51d 42 55 a-40c 3.3v (4) dc51e 42 55 a+25c dc51f 70 91 a+85c note 1: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: base i idle current is measured with core off, clock on, all modules off and all of the peripheral module disable (pmd) bits are set. 3: on-chip voltage regulator disabled (disvreg tied to v dd ). 4: on-chip voltage regulator enabled (disvreg tied to v ss ).
pic24fj64ga004 family ds39881b-page 228 preliminary ? 2007 microchip technology inc. table 26-6: dc characteristics: power-down current (i pd ) dc characteristics standard operating conditions: 2.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial parameter no. typical (1) max units conditions power-down current (i pd ): pmd bits are set, vregs bit is ? 0 ? (2) dc60 .1 1 a-40c 2.0v (3) base power-down current (5) dc60a .15 1 a+25c dc60b 3.7 12 a+85c dc60c .2 1 a-40c 2.5v (3) dc60d .25 1 a+25c dc60e 4.2 25 a+85c dc60f 3.3 9 a-40c 3.3v (4) dc60g 3.5 10 a+25c dc60h 9 30 a+85c dc61 1.75 3 a-40c 2.0v (3) watchdog timer current: i wdt (5) dc61a 1.75 3 a+25c dc61b 1.75 3 a+85c dc61c 2.4 4 a-40c 2.5v (3) dc61d 2.4 4 a+25c dc61e 2.4 4 a+85c dc61f 2.8 5 a-40c 3.3v (4) dc61g 2.8 5 a+25c dc61h 2.8 5 a+85c dc62 8 16 a-40c 2.0v (3) rtcc + timer1 w/32 khz crystal: rtcc i ti 32 (5) dc62a 12 16 a+25c dc62b 12 16 a+85c dc62c 9 16 a-40c 2.5v (3) dc62d 12 16 a+25c dc62e 12.5 16 a+85c dc62f 10.3 18 a-40c 3.3v (4) dc62g 13.4 18 a+25c dc62h 14.2 18 a+85c note 1: data in the typical column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: base i pd is measured with all peripherals and clocks shut down. all i/os are configured as inputs and pulled high. wdt, etc., are all switched off. 3: on-chip voltage regulator disabled (disvreg tied to v dd ). 4: on-chip voltage regulator enabled (disvreg tied to v ss ). 5: the current is the additional current consumed when the module is enabled. this current should be added to the base i pd current.
? 2007 microchip technology inc. preliminary ds39881b-page 229 pic24fj64ga004 family table 26-7: dc characteristics: i/o pin input specifications dc characteristics standard operating conditions: 2.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. sym characteristic min typ (1) max units conditions v il input low voltage di10 i/o pins v ss ? 0.2 v dd v di11 pmp pins v ss ?0.15 v dd v pmpttl = 1 di15 mclr v ss ? 0.2 v dd v di16 osci (xt mode) v ss ? 0.2 v dd v di17 osci (hs mode) v ss ? 0.2 v dd v di18 sdax, sclx v ss ? 0.3 v dd v smbus disabled di19 sdax, sclx v ss ? 0.8 v smbus enabled v ih input high voltage di20 i/o pins: with analog functions digital only 0.8 v dd 0.8 v dd ? ? v dd 5.5 v v di21 pmp pins: with analog functions digital only 0.24 v dd + 0.8 0.24 v dd + 0.8 ? ? v dd 5.5 v v pmpttl = 1 di25 mclr 0.8 v dd ?v dd v di26 osci (xt mode) 0.7 v dd ?v dd v di27 osci (hs mode) 0.7 v dd ?v dd v di28 sdax, sclx 0.7 v dd ?v dd v smbus disabled di29 sdax, sclx 2.1 ? v dd v smbus enabled, 2.5v v pin v dd di30 i cnpu cnxx pull-up current 50 250 400 av dd = 3.3v, v pin = v ss i il input leakage current (2,3) di50 i/o ports ? ? + 1 av ss v pin v dd , pin at high-impedance di51 analog input pins ? ? + 1 av ss v pin v dd , pin at high-impedance di55 mclr ??+ 1 av ss v pin v dd di56 osci ? ? + 1 av ss v pin v dd , xt and hs modes note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin.
pic24fj64ga004 family ds39881b-page 230 preliminary ? 2007 microchip technology inc. table 26-10: internal voltag e regulator specifications table 26-8: dc characteristics: i/o pin output specifications dc characteristics standard operating conditions: 2.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. sym characteristic min typ (1) max units conditions v ol output low voltage do10 i/o ports ? ? 0.4 v i ol = 8.5 ma, v dd = 3.6v ??0.4vi ol = 5.0 ma, v dd = 2.0v do16 osco/clko ? ? 0.4 v i ol = 8.5 ma, v dd = 3.6v ??0.4vi ol = 5.0 ma, v dd = 2.0v v oh output high voltage do20 i/o ports 3 ? ? v i oh = -3.0 ma, v dd = 3.6v 1.8 ? ? v i oh = -1.5 ma, v dd = 2.0v do26 osco/clko 3 ? ? v i oh = -3.0 ma, v dd = 3.6v 1.8 ? ? v i oh = -1.5 ma, v dd = 2.0v note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. table 26-9: dc characteristics: program memory dc characteristics standard operating conditions: 2.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. sym characteristic min typ (1) max units conditions program flash memory d130 e p cell endurance 10000 ? ? e/w -40 c to +85 c d131 v pr v dd for read v min ?3.6vv min = minimum operating voltage d132b v pew v dd for self-timed write v min ?3.6vv min = minimum operating voltage d133a t iw self-timed write cycle time ?3 ?ms d134 t retd characteristic retention 20 ? ? year provided no other specifications are violated d135 i ddp supply current during programming ?7 ?ma note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. operating conditions: -40c < t a < +85c (unless otherwise stated) param no. symbol characteristics min typ max units comments v rgout regulator output voltage ? 2.5 ? v c efc external filter capacitor value 4.7 10 ? f series resistance < 3 ohm recommended; < 5 ohm required. t vreg ?10? s disvreg = v ss t pwrt ? 64 ? ms disvreg = v dd
? 2007 microchip technology inc. preliminary ds39881b-page 231 pic24fj64ga004 family 26.2 ac characteristics and timing parameters the information contained in this section defines the pic24fj64ga family ac characteristics and timing parameters. table 26-11: temperature and voltage specifications ? ac figure 26-2: load conditions for device timing specifications table 26-12: capacitive loading requirements on output pins ac characteristics standard operating conditions: 2.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial operating voltage v dd range as described in section 26.1 ?dc characteristics? . param no. symbol characteristic min typ (1) max units conditions do50 c osc 2 osco/clko pin ? ? 15 pf in xt and hs modes when external clock is used to drive osci. do56 c io all i/o pins and osco ? ? 50 pf ec mode. do58 c b sclx, sdax ? ? 400 pf in i 2 c? mode. note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. v dd /2 c l r l pin pin v ss v ss c l r l = 464 c l = 50 pf for all pins except osco 15 pf for osco output load condition 1 ? for all pins except osco load condition 2 ? for osco
pic24fj64ga004 family ds39881b-page 232 preliminary ? 2007 microchip technology inc. figure 26-3: external clock timing osci clko q4 q1 q2 q3 q4 q1 os20 os25 os30 os30 os40 os41 os31 os31 q1 q2 q3 q4 q2 q3 table 26-13: external clock timing requirements ac characteristics standard operating conditions: 2.50 to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. sym characteristic min typ (1) max units conditions os10 f osc external clki frequency (external clocks allowed only in ec mode) dc 4 ? ? 32 8 mhz mhz ec ecpll oscillator frequency 3 3 10 31 ? ? ? ? 10 8 32 33 mhz mhz mhz khz xt xtpll hs sosc os20 t osc t osc = 1/f osc ? ? ? ? see parameter os10 for f osc value os25 t cy instruction cycle time (2) 62.5 ? dc ns os30 tosl, to s h external clock in (osci) high or low time 0.45 x t osc ??nsec os31 tosr, to s f external clock in (osci) rise or fall time ? ? 20 ns ec os40 tckr clko rise time (3) ? 6 10 ns os41 tckf clko fall time (3) ? 6 10 ns note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: instruction cycle period (t cy ) equals two times the input oscillator time base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ?min.? values with an external clock applied to the osci/clki pin. when an external clock input is used, the ?max.? cycle time limit is ?dc? (no clock) for all devices. 3: measurements are taken in ec mode. the clko signal is measured on the osco pin. clko is low for the q1-q2 period (1/2 t cy ) and high for the q3-q4 period (1/2 t cy ).
? 2007 microchip technology inc. preliminary ds39881b-page 233 pic24fj64ga004 family table 26-14: pll clock ti ming specifications (v dd = 2.0v to 3.6v) ac characteristics standard operating conditions: 2.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. sym characteristic (1) min typ (2) max units conditions os50 f plli pll input frequency range (2) 3 ? 8 mhz ecpll, hspll, xtpll modes os51 f sys on-chip vco system frequency 8?32mhz os52 t lock pll start-up time (lock time) ?? 2ms os53 d clk clko stability (jitter) -2 1 2 % measured over 100 ms period note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. table 26-15: ac characteristics: internal rc accuracy ac characteristics standard operating conditions: 2.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. characteristic min typ max units conditions internal frc accuracy @ 8 mhz (1) f20 frc -2 ? 2 % +25c -5 ? 5 % -40c t a +85c note 1: frequency calibrated at 25c and 3.3v. osctun bits can be used to compensate for temperature drift. table 26-16: internal rc accuracy ac characteristics standard operating conditions: 2.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. characteristic min typ max units conditions lprc @ 31 khz (1) f21 -15 ? 15 % +25c -15 ? 15 % -40c t a +85c note 1: change of lprc frequency as v dd changes.
pic24fj64ga004 family ds39881b-page 234 preliminary ? 2007 microchip technology inc. figure 26-4: clko and i/o timing characteristics note: refer to figure 26-2 for load conditions. i/o pin (input) i/o pin (output) di35 old value new value di40 do31 do32 table 26-17: clko and i/o timing requirements ac characteristics standard operating conditions: 2.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. sym characteristic min typ (1) max units conditions do31 t io r port output rise time ? 10 25 ns do32 t io f port output fall time ? 10 25 ns di35 t inp intx pin high or low time (output) 20 ? ? ns di40 t rbp cnx high or low time (input) 2??t cy note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated.
? 2007 microchip technology inc. preliminary ds39881b-page 235 pic24fj64ga004 family table 26-18: adc module specifications ac characteristics standard operating conditions: 2.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c param no. symbol characteristic min. typ max. units conditions device supply ad01 av dd module v dd supply greater of v dd ? 0.3 or 2.0 ?lesser of v dd + 0.3 or 3.6 v ad02 av ss module v ss supply v ss ? 0.3 ? v ss + 0.3 v reference inputs ad05 v refh reference voltage high av ss + 1.7 ? av dd v ad06 v refl reference voltage low av ss ?av dd ? 1.7 v ad07 v ref absolute reference voltage av ss ? 0.3 ? av dd + 0.3 v analog input ad10 v inh -v inl full-scale input span v refl ?v refh v (note 2) ad11 v in absolute input voltage av ss ? 0.3 ? av dd + 0.3 v ? ad17 r in recommended impedance of analog voltage source ? ? 2.5k 10-bit adc accuracy ad20b nr resolution ? 10 ? bits ad21b inl integral nonlinearity ? 1 <2 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3v ad22b dnl differential nonlinearity ? 1 <1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3v ad23b g err gain error ? 1 3 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3v ad24b e off offset error ? 1 2 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3v ad25b ? monotonicity (1) ? ? ? ? guaranteed note 1: the adc conversion result never decreases with an increase in the input voltage and has no missing codes. 2: measurements taken with external v ref + and v ref - used as the adc voltage reference.
pic24fj64ga004 family ds39881b-page 236 preliminary ? 2007 microchip technology inc. table 26-19: adc conversion timing requirements (1) ac characteristics standard operating conditions: 2.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c param no. symbol characteristic min. typ max. units conditions clock parameters ad50 t ad adc clock period 133 ? ? ns t cy = 133 ns, ad1con3 in default state ad51 t rc adc internal rc oscillator period ? 250 ? ns note 1: because the sample caps will eventually lose charge, clock rates below 10 khz can affect linearity performance, especially at elevated temperatures.
? 2007 microchip technology inc. preliminary ds39881b-page 237 pic24fj64ga004 family 27.0 packaging information 27.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 28-lead soic (.300?) xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx yywwnnn example pic24fj16ga002/so 0710017 28-lead qfn xxxxxxxx xxxxxxxx yywwnnn example 24fj48ga 002/ml 0710017 3 e 3 e 28-lead spdip xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnnn example -i/sp pic24fj16ga002 0710017 3 e 28-lead ssop xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example 24fj16ga002 /ss 0710017 3 e
pic24fj64ga004 family ds39881b-page 238 preliminary ? 2007 microchip technology inc. xxxxxxxxxx 44-lead qfn xxxxxxxxxx xxxxxxxxxx yywwnnn 24fj32ga example 004-i/ml 0710017 44-lead tqfp xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn example 24fj32ga 004-i/pt 0710017 3 e 3 e
? 2007 microchip technology inc. preliminary ds39881b-page 239 pic24fj64ga004 family 27.2 package details the following sections give the technical details of the packages. 28-lead skinny plastic dual in-line (sp) ? 300 mil body [spdip] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. significant characteristic. 3. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010" per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units inches dimension limits min nom max number of pins n 28 pitch e .100 bsc top to seating plane a ? ? .200 molded package thickness a2 .120 .135 .150 base to seating plane a1 .015 ? ? shoulder to shoulder width e .290 .310 .335 molded package width e1 .240 .285 .295 overall length d 1.345 1.365 1.400 tip to seating plane l .110 .130 .150 lead thickness c .008 .010 .015 upper lead width b1 .040 .050 .070 lower lead width b .014 .018 .022 overall row spacing eb ? ? .430 note 1 n 12 d e1 e b c e l a2 e b b1 a1 a 3 microchip technology drawing c04-070b
pic24fj64ga004 family ds39881b-page 240 preliminary ? 2007 microchip technology inc. 28-lead plastic shrink small outline (ss) ? 5.30 mm body [ssop] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.20 mm per side. 3. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 28 pitch e 0.65 bsc overall height a ? ? 2.00 molded package thickness a2 1.65 1.75 1.85 standoff a1 0.05 ? ? overall width e 7.40 7.80 8.20 molded package width e1 5.00 5.30 5.60 overall length d 9.90 10.20 10.50 foot length l 0.55 0.75 0.95 footprint l1 1.25 ref lead thickness c 0.09 ? 0.25 foot angle 0 4 8 lead width b 0.22 ? 0.38 l l1 c a2 a1 a e e1 d n 1 2 note 1 b e microchip technology drawing c04-073b
? 2007 microchip technology inc. preliminary ds39881b-page 241 pic24fj64ga004 family 28-lead plastic small outline (so) ? wide, 7.50 mm body [soic] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. significant characteristic. 3. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15 mm per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 28 pitch e 1.27 bsc overall height a ? ? 2.65 molded package thickness a2 2.05 ? ? standoff a1 0.10 ? 0.30 overall width e 10.30 bsc molded package width e1 7.50 bsc overall length d 17.90 bsc chamfer (optional) h 0.25 ? 0.75 foot length l 0.40 ? 1.27 footprint l1 1.40 ref foot angle top 0 ? 8 lead thickness c 0.18 ? 0.33 lead width b 0.31 ? 0.51 mold draft angle top 5 ? 15 mold draft angle bottom 5 ? 15 c h h l l1 a2 a1 a note 1 12 3 b e e e1 d n microchip technology drawing c04-052b
pic24fj64ga004 family ds39881b-page 242 preliminary ? 2007 microchip technology inc. 28-lead plastic quad flat, no lead package (ml) ? 6x6 mm body [qfn] with 0.55 mm contact length notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. package is saw singulated. 3. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 28 pitch e 0.65 bsc overall height a 0.80 0.90 1.00 standoff a1 0.00 0.02 0.05 contact thickness a3 0.20 ref overall width e 6.00 bsc exposed pad width e2 3.65 3.70 4.20 overall length d 6.00 bsc exposed pad length d2 3.65 3.70 4.20 contact width b 0.23 0.30 0.35 contact length l 0.50 0.55 0.70 contact-to-exposed pad k 0.20 ? ? d exposed d2 e b k e2 e l n note 1 1 2 2 1 n a a1 a 3 top view bottom view pad microchip technology drawing c04-105b
? 2007 microchip technology inc. preliminary ds39881b-page 243 pic24fj64ga004 family 44-lead plastic quad flat, no lead package (ml) ? 8x8 mm body [qfn] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. package is saw singulated. 3. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 44 pitch e 0.65 bsc overall height a 0.80 0.90 1.00 standoff a1 0.00 0.02 0.05 contact thickness a3 0.20 ref overall width e 8.00 bsc exposed pad width e2 6.30 6.45 6.80 overall length d 8.00 bsc exposed pad length d2 6.30 6.45 6.80 contact width b 0.25 0.30 0.38 contact length l 0.30 0.40 0.50 contact-to-exposed pad k 0.20 ? ? d exposed pad d2 e b k l e2 2 1 n note 1 2 1 e n bottom view top view a 3 a1 a microchip technology drawing c04-103b
pic24fj64ga004 family ds39881b-page 244 preliminary ? 2007 microchip technology inc. 44-lead plastic thin quad flatpack (pt) ? 10x10x1 mm body, 2.00 mm footprint [tqfp] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. chamfers at corners are optional; size may vary. 3. dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.25 mm per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of leads n 44 lead pitch e 0.80 bsc overall height a ? ? 1.20 molded package thickness a2 0.95 1.00 1.05 standoff a1 0.05 ? 0.15 foot length l 0.45 0.60 0.75 footprint l1 1.00 ref foot angle 0 3.5 7 overall width e 12.00 bsc overall length d 12.00 bsc molded package width e1 10.00 bsc molded package length d1 10.00 bsc lead thickness c 0.09 ? 0.20 lead width b 0.30 0.37 0.45 mold draft angle top 11 12 13 mold draft angle bottom 11 12 13 a e e1 d d1 e b note 1 note 2 n 12 3 c a1 l a2 l1 microchip technology drawing c04-076b
? 2007 microchip technology inc. preliminary ds39881b-page 245 pic24fj64ga004 family appendix a: revision history revision a (march 2007) original data sheet for the pic24fj64ga004 family of devices. revision b (march 2007) changes to table 26-8; pacakaging diagrams updated.
pic24fj64ga004 family ds39881b-page 246 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds39881b-page 247 pic24fj64ga004 family index a a/d converter ................................................................... 185 ac characteristics .......................................................... 229 internal rc accuracy........................................ 233 load conditions ........................................................ 231 temperature and voltage specifications .................. 231 alternate interrupt vector table (aivt) .............................. 53 arithmetic logic unit (alu)................................................. 21 assembler mpasm assembler................................................... 210 b baud rate error calculation (brgh = 0) ......................... 154 block diagrams 10-bit high-speed a/d converter............................. 186 16-bit timer1 module................................................ 117 8-bit multiplexed address and data application ........................................................ 170 accessing program memory with table instructions ............................................... 39 addressable parallel slave port ............................... 168 comparator i/o operating modes............................. 195 comparator voltage reference ................................ 199 connections for on-chip voltage regulator............. 207 device clock ............................................................... 87 i 2 c............................................................................. 144 input capture ............................................................ 125 lcd control .............................................................. 170 legacy parallel slave port........................................ 168 master mode, demultiplexed addressing ................. 168 master mode, fully multiplexed addressing ............. 169 master mode, partially multiplexed addressing ........ 169 multiplexed addressing application .......................... 169 output compare module........................................... 130 parallel eeprom (up to 11-bit address, 16-bit data)....................................................... 170 parallel eeprom (up to 11-bit address, 8-bit data)......................................................... 170 partially multiplexed addressing application ............ 169 pic24f cpu core ...................................................... 18 pic24fj64ga004 family (general) ........................... 10 pmp module ............................................................. 161 program space visibility operation ............................ 40 reset system.............................................................. 47 rtcc ........................................................................ 171 shared port structure ................................................. 97 spi ............................................................................ 134 spi master, frame master connection..................... 141 spi master, frame slave connection....................... 141 spi master/slave connection (enhanced buffer modes) ................................. 140 spi master/slave connection (standard mode) ............................................... 140 spi slave, frame master connection....................... 141 spi slave, frame slave connection......................... 141 timer2 and timer4 (16-bit synchronous)................. 121 timer2/3 and timer4/5 (32-bit)................................. 120 timer3 and timer5 (16-bit asynchronous) ............... 121 uart ........................................................................ 153 watchdog timer (wdt) ............................................ 208 c c compilers mplab c18.............................................................. 212 mplab c30.............................................................. 212 clock switching and clock frequency.................................................. 95 enabling...................................................................... 93 operation.................................................................... 93 oscillator sequence .................... ............................... 94 code examples basic code sequence for clock switching ................ 94 configuring uart1 input and output functions .............................................. 102 erasing a program memory block.............................. 44 initiating a programming sequence ........................... 45 loading write buffers ................................................. 45 port write/read .......................................................... 98 pwrsav instruction syntax ...................................... 95 setting the rtcwren bit........................................ 172 comparator module .......................................................... 195 comparator voltage reference ........................................ 199 configuring ............................................................... 199 configuration bits ............................................................. 201 configuration register protection..................................... 209 configuring analog port pins.............................................. 98 core features....................................................................... 7 16-bit architecture ........................................................ 7 easy migration.............................................................. 8 oscillator options, features ......................................... 7 power-saving technology............................................ 7 cpu .................................................................................... 17 control registers........................................................ 20 programmer?s model .................................................. 19 crc example setup ......................................................... 183 operation in power save modes.............................. 184 overview................................................................... 183 registers .................................................................. 181 user interface ........................................................... 184 customer change notification service............................. 251 customer notification service .......................................... 251 customer support............................................................. 251 d data memory address space ........................................................... 25 width .................................................................. 25 memory map for pic24fj64ga004 family................ 25 near data space ........................................................ 26 organization and alignment ....................................... 26 sfr space ................................................................. 26 software stack ........................................................... 37 dc characteristics............................................................ 224 i/o pin input specifications ...................................... 229 i/o pin output specifications.................................... 230 idle current (i idle ) .................................................... 227 operating current (i dd ) ............................................ 224 power-down current (i pd )........................................ 228 program memory...................................................... 230 temperature and voltage specifications.................. 225 development support ....................................................... 211 disvreg pin ................................................................... 207
pic24fj64ga004 family ds39881b-page 248 preliminary ? 2007 microchip technology inc. e electrical characteristics................................................... 223 absolute maximum ratings ...................................... 223 equations a/d conversion clock period ................................... 192 calculating the pwm period ..................................... 128 calculation for maximum pwm resolution............... 128 relationship between device and spi clock speed............................................... 142 uart baud rate with brgh = 0 ............................. 154 uart baud rate with brgh = 1 ............................. 154 errata .................................................................................... 5 f flash configuration words.......................................... 24, 201 flash program memory....................................................... 41 control registers ........................................................ 42 enhanced icsp .......................................................... 42 jtag operation .......................................................... 42 operations .................................................................. 42 programming algorithm .............................................. 44 rtsp operation.......................................................... 42 table instructions........................................................ 41 fscm and device resets ...................................................... 51 delay for crystal and pll clock sources ................... 51 i i/o ports .............................................................................. 97 parallel i/o (pio)......................................................... 97 write/read timing ...................................................... 98 i 2 c clock rates............................................................... 145 communicating as master in a single master environment.......................................... 143 setting baud rate when operating as bus master........................................................ 145 slave address masking ............................................ 145 implemented interrupt vectors (table)................................. 55 in-circuit debugger ........................................................... 209 in-circuit serial programming (icsp) ............................... 209 input capture .................................................................... 125 registers................................................................... 126 input change notification.................................................... 98 instruction set overview ................................................................... 217 summary................................................................... 215 inter-integrated circuit (i2c) ............................................. 143 internal rc oscillator use with wdt ........................................................... 208 internet address................................................................ 251 interrupt control and status registers................................ 56 iecx ............................................................................ 56 ifsx............................................................................. 56 intcon1, intcon2 .................. ................................ 56 ipcx ............................................................................ 56 interrupt controller .............................................................. 53 interrupt setup procedures ................................................. 85 initialization ................................................................. 85 interrupt disable.......................................................... 85 interrupt service routine (isr)................................... 85 trap service routine (tsr)........................................ 85 interrupt vector table (ivt) ................................................ 53 interrupts coincident with power save instructions............ 96 l low-voltage detection...................................................... 207 m memory organization ......................................................... 23 microchip internet web site.............................................. 251 mplab asm30 assembler, linker, librarian ................... 212 mplab icd 2 in-circuit debugger ................................... 213 mplab ice 2000 high-performance universal in-circuit emulator .................................... 213 mplab integrated development environment software .............................................. 211 mplab pm3 device programmer .................................... 213 mplab real ice in-circuit emulator system ................ 213 mplink object linker/mplib object librarian ................ 212 o open-drain configuration................................................... 98 oscillator configuration ................. ..................................... 87 clock switching mode configuration bits ................... 88 control registers ........................................................ 89 clkdiv............................................................... 89 osccon............................................................ 89 osctun ............................................................ 89 output compare ............................................................... 127 registers .................................................................. 131 p packaging ......................................................................... 235 details....................................................................... 239 marking ..................................................................... 237 parallel master port (pmp) ............................................... 161 peripheral pin select .......................................................... 99 available peripherals .................................................. 99 available pins ............................................................. 99 considerations.......................................................... 102 controlling .................................................................. 99 registers .................................................................. 103 picstart plus development programmer..................... 214 pinout descriptions pic24fj64ga004 family ........................................... 11 por and long oscillator start-up times ........................... 51 power-saving features ...................................................... 95 power-saving modes idle mode............................................................ 96 doze mode ................................................................. 96 instruction-based........................................................ 95 sleep mode ................................................................ 95 program address space..................................................... 23 memory map for pic24fj64ga004 family devices ................................................... 23 program and data memory spaces interfacing ................................................................... 37 program memory data access using table instructions ........................ 39 hard memory vectors................................................. 24 interrupt vector ........................................................... 24 organization ............................................................... 24 reading data using program space visibility............ 40 reset vector............................................................... 24 table instructions tblrdh ............................................................. 39 tblrdl.............................................................. 39
? 2007 microchip technology inc. preliminary ds39881b-page 249 pic24fj64ga004 family program space address construction.................................................. 38 addressing .................................................................. 37 data access from, address generation...................... 38 program verification and code protection........................ 209 programmer?s model........................................................... 17 pulse-width modulation mode .......................................... 128 duty cycle................................................................. 128 period........................................................................ 128 r reader response ............................................................. 252 register map adc ............................................................................ 33 clock control .............................................................. 36 cpu core.................................................................... 27 crc ............................................................................ 34 dual comparator......................................................... 34 i 2 c............................................................................... 30 icn.............................................................................. 27 input capture .............................................................. 29 interrupt controller ...................................................... 28 nvm ............................................................................ 36 output compare ......................................................... 30 pad configuration ....................................................... 32 parallel master/slave port .......................................... 33 peripheral pin select .................................................. 35 pmd ............................................................................ 36 porta........................................................................ 32 portb........................................................................ 32 portc ....................................................................... 32 real-time clock and calendar................................... 34 spi .............................................................................. 31 timer........................................................................... 29 uart .......................................................................... 31 registers ad1chs0 (a/d input select) .................................... 190 ad1con1 (a/d control 1) ........................................ 187 ad1con2 (a/d control 2) ........................................ 188 ad1con3 (a/d control 3) ........................................ 189 ad1cssl (a/d input scan select) ........................... 191 ad1pcfg (a/d port configuration).......................... 191 alcfgrpt (alarm configuration)............................ 175 alminsec (alarm minutes and seconds value) ................................................ 179 almthdy (alarm month and day value) ................ 178 alwdhr (alarm weekday and hours value) ..................................................... 178 clkdiv (clock divider) .............................................. 92 cmcon (comparator control) ................................. 196 corcon (cpu control) ...................................... 21, 59 crccon (crc control) .......................................... 181 crcxor (crc xor polynomial)............................ 182 cvrcon (comparator voltage reference control) ........................................... 200 cw1 (flash configuration word 1)........................... 202 cw2 (flash configuration word 2)........................... 204 devid (device id) .................................................... 205 devrev (device revision) ...................................... 206 i2cxcon (i2cx control) ........................................... 147 i2cxmsk (i2cx slave mode address mask) ............ 151 i2cxstat (i2cx status) ........................................... 149 icxcon (input capture x control) ............................ 126 iec0 (interrupt enable control 0) ............................... 65 iec1 (interrupt enable control 1) ............................... 66 iec2 (interrupt enable control 2) ............................... 67 iec3 (interrupt enable control 3) ............................... 68 iec4 (interrupt enable control 4) ............................... 69 ifs0 (interrupt flag status 0) ..................................... 60 ifs1 (interrupt flag status 1) ..................................... 61 ifs2 (interrupt flag status 2) ..................................... 62 ifs3 (interrupt flag status 3) ..................................... 63 ifs4 (interrupt flag status 4) ..................................... 64 intcon1 (interrupt control 1) ................................... 58 intcon2 (interrupt control 2) ................................... 59 ipc0 (interrupt priority control 0) ............................... 70 ipc1 (interrupt priority control 1) ............................... 71 ipc10 (interrupt priority control 10) ........................... 80 ipc11 (interrupt priority control 11) ........................... 80 ipc12 (interrupt priority control 12) ........................... 81 ipc15 (interrupt priority control 15) ........................... 82 ipc16 (interrupt priority control 16) ........................... 83 ipc18 (interrupt priority control 18) ........................... 84 ipc2 (interrupt priority control 2) ............................... 72 ipc3 (interrupt priority control 3) ............................... 73 ipc4 (interrupt priority control 4) ............................... 74 ipc5 (interrupt priority control 5) ............................... 75 ipc6 (interrupt priority control 6) ............................... 76 ipc7 (interrupt priority control 7) ............................... 77 ipc8 (interrupt priority control 8) ............................... 78 ipc9 (interrupt priority control 9) ............................... 79 minsec (minutes and seconds value) ................... 177 mthdy (month and day value)............................... 176 ocxcon (output compare x control) ..................... 131 osccon (oscillator control)..................................... 90 padcfg1 (pad configuration control)............ 167, 174 pmaddr (parallel port address)............................. 165 pmaen (parallel port enable).................................. 165 pmcon (parallel port control)................................. 162 pmmode (parallel port mode) ................................ 164 pmstat (parallel port status)................................. 166 rcfgcal (rtcc calibration and configuration) ............................................ 173 rcon (reset control)................................................ 48 rpinr0 (peripheral pin select input 0) ................... 103 rpinr1 (peripheral pin select input 1) ................... 103 rpinr11 (peripheral pin select input 11) ............... 106 rpinr18 (peripheral pin select input 18) ............... 107 rpinr19 (peripheral pin select input 19) ............... 107 rpinr20 (peripheral pin select input 20) ............... 108 rpinr21 (peripheral pin select input 21) ............... 108 rpinr22 (peripheral pin select input 22) ............... 109 rpinr23 (peripheral pin select input 23) ............... 109 rpinr3 (peripheral pin select input 3) ................... 104 rpinr4 (peripheral pin select input 4) ................... 104 rpinr7 (peripheral pin select input 7) ................... 105 rpinr8 (peripheral pin select input 8) ................... 105 rpinr9 (peripheral pin select input 9) ................... 106 rpor0 (peripheral pin select output 0) ................. 110 rpor1 (peripheral pin select output 1) ................. 110 rpor10 (peripheral pin select output 10) ............. 115 rpor11 (peripheral pin select output 11) ............. 115 rpor12 (peripheral pin select output 12) ............. 116 rpor2 (peripheral pin select output 2) ................. 111 rpor3 (peripheral pin select output 3) ................. 111 rpor4 (peripheral pin select output 4) ................. 112 rpor5 (peripheral pin select output 5) ................. 112 rpor6 (peripheral pin select output 6) ................. 113 rpor7 (peripheral pin select output 7) ................. 113 rpor8 (peripheral pin select output 8) ................. 114 rpor9 (peripheral pin select output 9) ................. 114
pic24fj64ga004 family ds39881b-page 250 preliminary ? 2007 microchip technology inc. spixcon1 (spix control 1)...................................... 136 spixcon2 (spix control 2)...................................... 137 spixstat (spix status and control) ....................... 135 sr (alu status in cpu) ......................................... 57 sr (alu status) ..................................................... 20 t1con (timer1 control)........................................... 118 txcon (timer2/4 control)........................................ 122 tycon (timer3/5 control)........................................ 123 uxmode (uartx mode) .......................................... 156 uxrxreg (uartx receive).................................... 160 uxsta (uartx status and control) ......................... 158 uxtxeg (uartx transmit)...................................... 160 wkdyhr (weekday and hours value) .................... 177 year (year value) ................................................... 176 reset sequence.................................................................. 53 resets ................................................................................. 47 clock source selection ............................................... 49 device times .............................................................. 49 revision history ................................................................ 245 rtcc alarm......................................................................... 180 configuring........................................................ 180 interrupt............................................................. 180 alrmval register mappings .................................. 178 calibration ................................................................. 179 control registers ...................................................... 173 module registers ...................................................... 172 mapping ............................................................ 172 rtcval register mapping....................................... 176 write lock ................................................................. 172 s selective peripheral module control................................... 96 serial peripheral interface (spi) ....................................... 133 setup for continuous output pulse generation................ 127 setup for single output pulse generation ........................ 127 software simulator (mplab sim)..................................... 212 software stack pointer, frame pointer call stack frame...................................................... 37 special features ............................................................... 201 code protection ........................................................ 201 flexible configuration ............................................... 201 in-circuit emulation................................................... 201 in-circuit serial programming (icsp) ....................... 201 jtag boundary scan interface ................................ 201 watchdog timer (wdt) ............................................ 201 special function register reset states.............................. 51 symbols used in opcode descriptions............................. 216 t timer1 module.................................................................. 117 timer2/3 module............................................................... 119 timer4/5 module............................................................... 119 timing diagrams clko and i/o ........................................................... 234 external clock........................................................... 232 timing requirements 12-bit a/d conversion .............................................. 236 capacitive loading on output pin ............................ 231 clko and i/o ........................................................... 234 external clock........................................................... 232 timing specifications pll clock ................................................................. 233 tracking mode .................................................................. 207 u uart baud rate generator (brg) .................................... 154 infrared support........................................................ 155 irda built-in encoder and decoder........................... 155 external support, clock output ........................ 155 operation of uxcts and uxrts control pins ...................................................... 155 receiving 8-bit or 9-bit data mode ................................... 155 transmitting 8-bit data mode ................................................ 155 9-bit data mode................................................ 155 break and sync sequence ............................... 155 universal asynchronous receiver transmitter (uart) .................................................. 153 v v ddcore /v cap pin ........................................................... 207 voltage regulator (on-chip) ............................................ 207 and bor ................................................................... 208 and por ................................................................... 207 low-voltage detection (lvd) ................................... 207 tracking mode .......................................................... 207 w watchdog timer (wdt).................................................... 208 control register........................................................ 209 programming considerations ................................... 208 www address ................................................................. 251 www, on-line support .................... ................................... 5
? 2007 microchip technology inc. preliminary ds39881b-page 251 pic24fj64ga004 family the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com
pic24fj64ga004 family ds39881b-page 252 preliminary ? 2007 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds39881b pic24fj64ga004 family 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2007 microchip technology inc. preliminary ds39881b-page 253 pic24fj64ga004 family product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . architecture 24 = 16-bit modified harvard without dsp flash memory family fj = flash program memory product group ga0 = general purpose microcontrollers pin count 02 = 28-pin 04 = 44-pin temperature range i = -40 c to +85 c (industrial) package sp = spdip so = soic ss = ssop ml = qfn pt = tqfp pattern three-digit qtp, sqtp, code or special requirements (blank otherwise) es = engineering sample examples: a) pic24fj32ga002-i/ml: general purpose pic24f, 32-kbyte program memory, 28-pin, industrial temp., qfn package. b) pic24fj64ga004-i/pt: general purpose pic24f, 64-kbyte program memory, 44-pin, industrial temp., tqfp package. microchip trademark architecture flash memory family program memory size (kb) product group pin count temperature range package pattern pic 24 fj 64 ga0 04 t - i / pt - xxx tape and reel flag (if applicable)
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